Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 8171449 | Generating sequence diagrams using call trees A software tool is provided to analyze static source code. Source Code files are selected to define the project work space. A class and a method in the class are selected from said selected source code files. The tool generates a Call Tree as an ordered recursive se... | 05/01/2012 |
| 8146055 | Generating sequence diagrams using call trees A software tool is provided to analyze static source code. Source Code files are selected to define the project work space. A class and a method in the class are selected from said selected source code files. The tool generates a Call Tree as an ordered recursive se... | 03/27/2012 |
| 8141073 | Generating sequence diagrams using call trees A software tool is provided to analyze static source code. Source Code files are selected to define the project work space. A class and a method in the class are selected from said selected source code files. The tool generates a Call Tree as an ordered recursive se... | 03/20/2012 |
| 8134225 | Quad flat no-lead chip carrier with standoff A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second le... | 03/13/2012 |
| 8097492 | Method and manufacture of silicon based package and devices manufactured thereby A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures... | 01/17/2012 |
| 8086734 | Method of autonomic representative selection in local area networks A method and apparatus for selecting a client computer as a relay server to rebroadcast common application information that is broadcast from a server system over a network. The client computer is selected randomly to rebroadcast the User Datagram Protocol (UDP) inf... | 12/27/2011 |
| 8039314 | Metal adhesion by induced surface roughness Back side metal (BSM) delamination induced by chip dicing of silicon wafers is avoided by roughening the polished silicon surface at chip edges by etching. The Thru-Silicon-Via (TSV) structures used in 3D chip integration is masked at the back side from roughening t... | 10/18/2011 |
| 7969405 | Double-sided LCD panel There is disclosed a double-sided liquid crystal display (LCD) panel which includes a first polymer dispersed liquid crystal (PDLC) layer configured to be responsive to an applied DC voltage for making the first PDLC layer substantially transparent; a center liquid ... | 06/28/2011 |
| 7919834 | Edge seal for thru-silicon-via technology One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier lay... | 04/05/2011 |
| 7886435 | High performance chip carrier substrate A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, ... | 02/15/2011 |
| 7864072 | System and method for automatically adjusting traffic light A system, program product and method for automatically adjusting the traffic light of a traffic light controlled intersection. Personal data relative to a pedestrian cross walking the intersection, including walking speed, and the current speed of a vehicle approach... | 01/04/2011 |
| 7863526 | High performance chip carrier substrate A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, ... | 01/04/2011 |
| 7861209 | Method for interlayer and yield based optical proximity correction An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. ... | 12/28/2010 |
| 7855442 | Silicon based package A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures... | 12/21/2010 |
| 7839163 | Programmable through silicon via Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adja... | 11/23/2010 |
| 7824961 | Stacked imager package An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip... | 11/02/2010 |
| 7820521 | Conductive through via structure and process for electronic device carriers Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form a... | 10/26/2010 |
| 7712069 | Method for interlayer and yield based optical proximity correction An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. ... | 05/04/2010 |
| 7703199 | Method to accommodate increase in volume expansion during solder reflow Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of th... | 04/27/2010 |
| 7666775 | Split poly-SiGe/poly-Si alloy gate stack A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer o... | 02/23/2010 |
| 7645701 | Silicon-on-insulator structures for through via in silicon carriers A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buri... | 01/12/2010 |
| 7560950 | Packaging reliability superchips A test chip module for testing the integrity of the flp chip solder ball interconnections between chip and substrate. The interconnections, are thermally stressed through an array of individual heaters formed in a layer of chip metallurgy to provide a uniform and ub... | 07/14/2009 |
| 7521798 | Stacked imager package An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip... | 04/21/2009 |
| 7506320 | Generating sequence diagrams using call trees A software tool is provided to analyze static source code. Source Code files are selected to define the project work space. A class and a method in the class are selected from said selected source code files. The tool generates a Call Tree as an ordered recursive se... | 03/17/2009 |
| 7488680 | Conductive through via process for electronic device carriers Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form a... | 02/10/2009 |
| 7465649 | Method of forming a split poly-SiGe/poly-Si alloy gate stack A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer o... | 12/16/2008 |
| 7454833 | High performance chip carrier substrate A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, ... | 11/25/2008 |
| 7408264 | SMT passive device noflow underfill methodology and structure An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. T... | 08/05/2008 |
| 7405106 | Quad flat no-lead chip carrier with stand-off A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second le... | 07/29/2008 |
| 7378336 | Split poly-SiGe/poly-Si alloy gate stack A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer o... | 05/27/2008 |
| 7361989 | Stacked imager package An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip... | 04/22/2008 |
| 7348261 | Wafer scale thin film package A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a c... | 03/25/2008 |
| 7348792 | Packaging reliability super chips A test chip module for testing the integrity of the flip chip solder ball interconnections between chip and substrate. The interconnections are thermally stressed through an array of individual heaters formed in a layer of chip metallurgy to provide a uniform and ub... | 03/25/2008 |
| 7334212 | Method for interlayer and yield based optical proximity correction An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. ... | 02/19/2008 |
| 7278207 | Method of making an electronic package An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of diele... | 10/09/2007 |
| 7252515 | Non-oriented wire in elastomer electrical contact A method and apparatus for interconnecting an electronic module to a substrate through resilient wire conductors in an interposer arrangement. A carrier layer of insulating material with an array of apertures, arranged to align with both the electrical pads on an el... | 08/07/2007 |
| 7250330 | Method of making an electronic package A method of making an electronic package is described, wherein a substrate is provided with a pattern of conductive pads and a portion of solder positioned on selected ones of the pattern of copper pads. The solder is then reflowed to form partial hemispherically sh... | 07/31/2007 |
| 7214886 | High performance chip carrier substrate A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, ... | 05/08/2007 |
| 7204697 | Non-oriented wire in elastomer electrical contact A method and apparatus for interconnecting an electronic module to a substrate through resilient wire conductors in an interposer arrangement. A carrier layer of insulating material with an array of apertures, arranged to align with both the electrical pads on an el... | 04/17/2007 |
| 7109592 | SMT passive device noflow underfill methodology and structure An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. T... | 09/19/2006 |
