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| Number | Title | Issue Date |
| 8138410 | Optical tandem photovoltaic cell panels A solar energy conversion device comprises a vertical stack of at least two panels stacked in a hierarchy from an upper panel to a lower panel with each of the panels including a matching array of solar cells having a different energy bandgap from other panels of so... | 03/20/2012 |
| 8101856 | Quantum well GaP/Si tandem photovoltaic cells Two junction solar energy conversion devices, i.e. photovoltaic cells have a bottom silicon N+/P/P+ photovoltaic cell and an upper GaP N+/P/P+ photovoltaic cell containing quantum well layers which extend the wavelength range over which the GaP cell absorbs light. T... | 01/24/2012 |
| 8076756 | Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep I... | 12/13/2011 |
| 7971166 | Method, system, and program product for automated verification of gating logic using formal verification Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testb... | 06/28/2011 |
| 7955955 | Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep I... | 06/07/2011 |
| 7923712 | Phase change memory element with a peripheral connection to a thin film electrode A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the ph... | 04/12/2011 |
| 7892956 | Methods of manufacture of vertical nanowire FET devices A vertical Field Effect Transistor (FET) comprising a vertical semiconductor nanowire is formed by the following steps. Create a columnar pore in a bottom dielectric layer formed on a bottom electrode. Fill the columnar pore by plating a vertical semiconductor nanow... | 02/22/2011 |
| 7837598 | Exercise bar with adjustable angle handles An exercise bar includes a pair of handles having proximal ends with at least one fulcrum hole extending through the proximal end of each thereof. A center plate has a periphery and a pair of pivot holes therethrough. One of a pair of pivot pins is inserted through ... | 11/23/2010 |
| 7825000 | Method for integration of magnetic random access memories with improved lithographic alignment to magnetic tunnel junctions A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of th... | 11/02/2010 |
| 7773220 | Method and system for collecting alignment data from coated chips or wafers A process and system for determining alignment data for partially obscured features on wafers or chips when a wafer or chip is substantially coated by an over bump applied material, e.g. a resin or film, and using that data to align the wafers or chips for subsequen... | 08/10/2010 |
| 7700993 | CMOS EPROM and EEPROM devices and programmable CMOS inverters A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thi... | 04/20/2010 |
| 7700425 | Raised source drain mosfet with amorphous notched gate cap layer with notch sidewalls passivated and filled with dielectric plug A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon l... | 04/20/2010 |
| 7661050 | Method and system for formal verification of partial good self test fencing structures The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method fo... | 02/09/2010 |
| 7642549 | Phase change memory cells delineated by regions of modified film resistivity A Phase Change Memory (PCM) cell structure comprises both a lower electrode composed of a PCM layer and a conductive encapsulating upper electrode layer. The PCM layer is protected from damage by the conductive encapsulating layer. Electrical isolation between adjac... | 01/05/2010 |
| 7577795 | Disowning cache entries on aging out of the entry Portions of data in a processor system are stored in a slower main memory and are transferred to a faster memory comprising a hierarchy of cache structures between one or more processors and the main memory. For a system with shared L2 cache(s) between the processor... | 08/18/2009 |
| 7559002 | Multi-thread parallel segment scan simulation of chip element performance A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring dat... | 07/07/2009 |
| 7550313 | Method for delineation of phase change memory (PCM) cells separated by PCM and upper electrode regions modified to have high film resistivity A method for forming a Phase Change Material (PCM) cell structure comprises forming both a lower electrode composed of a PCM layer and a conductive encapsulating upper electrode layer. The PCM is protected from damage by a conductive encapsulating layer. Electrical ... | 06/23/2009 |
| 7506287 | Method, system, and program product for pre-compile processing of hardware design language (HDL) source files A method includes pre-compilation operations on HDL source code files, creating a “make it” file, on demand processing of the HDL source code in an HDL source browser, and resolving overloaded function and operator calls in an HDL source code browser debugger. C... | 03/17/2009 |
| 7485516 | Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the subst... | 02/03/2009 |
| 7448008 | Method, system, and program product for automated verification of gating logic using formal verification Automated verification methodology parsing scripts auto generate testbench hardware design language, such as VHDL or Verilog, from the design source VHDL or Verilog. A formal verification model is then built comprising the testbench VHDL and the design under test. T... | 11/04/2008 |
| 7361950 | Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capac... | 04/22/2008 |
| 7344552 | Mechanical coupling device for removably attaching a gem or a crystal to an acupuncture needle or to a vibratory device for acupressure treatment and method of treatment therewith A mechanical coupling device is provided for temporarily interconnecting a gem or a crystal to be used for acupressure treatment to a vibration generating device. Alternatively a mechanical coupling device is provided for temporarily interconnecting the handle of an... | 03/18/2008 |
| 7205237 | Apparatus and method for selected site backside unlayering of si, GaAs, GaAlAsof SOI technologies for scanning probe microscopy and atomic force probing characterization Apparatus for exposure and probing of features in a semiconductor workpiece includes a hollow concentrator for covering a portion of the workpiece connected by a gas conduit to a supply of etchant gas. A stage supports and positions the semiconductor workpiece. Cont... | 04/17/2007 |
| 7180157 | Bipolar transistor with a very narrow emitter feature A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped intrinsic emitter formed in the surface of the intrinsic base. A... | 02/20/2007 |
| 7138685 | Vertical MOSFET SRAM cell A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on... | 11/21/2006 |
| 7132322 | Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET device Form a dielectric layer on a semiconductor substrate. Deposit an amorphous Si film or a poly-Si film on the dielectric layer. Then deposit a SiGe amorphous-Ge or polysilicon-Ge thin film theteover. Pattern and etch the SiGe film using a selective etch leaving the Si... | 11/07/2006 |
| 7129159 | Integrated dual damascene RIE process with organic patterning layer A dual damascene conductor structure is formed on a substrate with an exposed conductor on top covered by a buried cap, a dielectric layer (DL) and an organic layer (OL). Form a lower via hard mask layers over the OL and form a top trench patterning hard mask over t... | 10/31/2006 |
| 7045901 | Chip-on-chip connection with second chip located in rectangular open window hole in printed circuit board A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window ... | 05/16/2006 |
| 7012789 | Composite shared pole design for magnetoresistive merged heads A merged read/write magnetic recording head comprises a low magnetic moment first magnetic shield layer over a substrate. A read gap layer with a magnetoresistive head is formed over the first shield layer. A shared pole comprises a low magnetic moment second magnet... | 03/14/2006 |
| 7002214 | Ultra-thin body super-steep retrograde well (SSRW) FET devices A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer i... | 02/21/2006 |
| 6950353 | Cell data margin test with dummy cell A memory array includes a true bitline and a complementary bitline and a sense amplifier connected thereto; a row of normal cells with capacitors for data storage and bitline storage capacitors. A row of dummy cells with dummy cell capacitors is also provided. A clo... | 09/27/2005 |
| 6943409 | Trench optical device A semiconductor device is formed in on a semiconductor substrate starting with a first step, which is to form a wide trench and a narrow trench in the substrate. Then form a first electrode in the narrow trench by depositing a first fill material of a first conducti... | 09/13/2005 |
| 6939751 | Method and manufacture of thin silicon on insulator (SOI) with recessed channel An RSD FET device with a recessed channel is formed with a raised silicon sources and drains and a gate electrode structure formed on an SOI structure (a Si layer formed on a substrate) by the steps as follows. Form a SiGe layer over the Si layer and a RSD layer ove... | 09/06/2005 |
| 6930030 | Method of forming an electronic device on a recess in the surface of a thin film of silicon etched to a precise thickness A method for precise thinning to form a recess to a precise depth in a crystalline silicon layer, which can be used to form various devices, such as MOSFET devices, includes the following steps. Form a patterning mask with a window therethrough over the top surface ... | 08/16/2005 |
| 6884715 | Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby A method of forming a device including a conductor and a contact over a semiconductor substrate starts by depositing first dielectric and first hard mask layers on the substrate. Form a conductor slot through the hard mask and down into or through the first dielectr... | 04/26/2005 |
| 6878608 | Method of manufacture of silicon based package A silicon based package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including multilayer conductor pat... | 04/12/2005 |
| 6872620 | Trench capacitors with reduced polysilicon stress A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in t... | 03/29/2005 |
| 6864560 | Bipolar transistor structure with a shallow isolation extension region providing reduced parasitic capacitance A bipolar vertical transistor is formed in a silicon semiconductor substrate which has an upper surface with STI regions formed therein composed of a dielectric material formed in the substrate having inner ends and top surfaces. A doped collector region is formed i... | 03/08/2005 |
| 6858532 | Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The i... | 02/22/2005 |
| 6858903 | MOSFET device with in-situ doped, raised source and drain structures A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may... | 02/22/2005 |
