Quotables
"That the automobile has practically reached the limit of its development is suggested by the fact that during the past year no improvements of a radical nature have been introduced."
Scientific American ; Jan. 2 edition, 1909
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8053257 | Method for prediction of premature dielectric breakdown in a semiconductor The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for a layer within chips comprising a semiconductor wafer lot. If only one mode is calculated, that is the best calculated mode. If multipl... | 11/08/2011 |
| 8021974 | Structure and method for back end of the line integration An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the co... | 09/20/2011 |
| 7923836 | BLM structure for application to copper pad A microelectronic element and a related method for fabricating such is provided. The microelectronic element comprises a contact pad overlying a major surface of a substrate. The contact pad has a composition including copper at a contact surface. A passivation laye... | 04/12/2011 |
| 7745324 | Interconnect with recessed dielectric adjacent a noble metal cap The invention comprises a copper interconnect structure that includes a noble metal cap with dielectric immediately adjacent the copper/noble metal cap interface recessed from the noble metal cap. ... | 06/29/2010 |
| 7732922 | Simultaneous grain modulation for BEOL applications The invention is directed to an improved semiconductor structure, such that within the same insulating layer, Cu interconnects embedded within the same insulating level layer have a different Cu grain size than other Cu interconnects embedded within the same insulat... | 06/08/2010 |
| 7728372 | Method and structure for creation of a metal insulator metal capacitor The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of ... | 06/01/2010 |
| 7704876 | Dual damascene interconnect structures having different materials for line and via conductors Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those us... | 04/27/2010 |
| 7693324 | Optical surface inspection The present invention provides a method, an optical inspection apparatus as well as a computer program product for optical inspection of a surface. The optical inspection apparatus can be effectively applied for optical inspection of periodic structures on e.g. a se... | 04/06/2010 |
| 7692439 | Structure for modeling stress-induced degradation of conductive interconnects A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfac... | 04/06/2010 |
| 7662722 | Air gap under on-chip passive device A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic ... | 02/16/2010 |
| 7648891 | Semiconductor chip shape alteration The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a ... | 01/19/2010 |
| 7639032 | Structure for monitoring stress-induced degradation of conductive interconnects A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metal... | 12/29/2009 |
| 7615482 | Structure and method for porous SiCOH dielectric layers and adhesion promoting or etch stop layers having increased interfacial and mechanical strength Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductiv... | 11/10/2009 |
| 7596862 | Method of making a circuitized substrate A method of making the circuitized substrate. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall... | 10/06/2009 |
| 7585722 | Integrated circuit comb capacitor The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at... | 09/08/2009 |
| 7566593 | Fuse structure including cavity and methods for fabrication thereof A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed betwee... | 07/28/2009 |
| 7541679 | Exposed pore sealing post patterning Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric l... | 06/02/2009 |
| 7507591 | Methods of measurement and preparation of measurement structure of integrated circuit A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure f... | 03/24/2009 |
| 7503021 | Integrated circuit diagnosing method, system, and program product The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is gener... | 03/10/2009 |
| 7494915 | Back end interconnect with a shaped interface An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of th... | 02/24/2009 |
| 7492016 | Protection against charging damage in hybrid orientation transistors A chip includes a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. A SOI ... | 02/17/2009 |
| 7487153 | Locker manager for managing access to shared resources A method and system for controlling access to computer resources by multiple software components is described. A locker manager is provided, which is adapted to manage access to shared computer resources by independent software components. If a particular hardware r... | 02/03/2009 |
| 7474557 | MRAM array and access method thereof A magnetic random access memory (MRAM) array is disclosed herein in which a plurality of wordlines and a plurality of bitlines are provided in matrix form, the wordlines including read wordlines and write wordlines, and memory elements are provided at the intersecti... | 01/06/2009 |
| 7456636 | Test structures and method of defect detection using voltage contrast inspection Test structures and a method for voltage contrast (VC) inspection are disclosed. In one embodiment, the test structure includes: a gate stack that is grounded by a ground to maintain the gate stack in an off state during VC inspection, which allows NFET defect detec... | 11/25/2008 |
| 7456099 | Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines ... | 11/25/2008 |
| 7442650 | Methods of manufacturing semiconductor structures using RIE process A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a... | 10/28/2008 |
| 7428675 | Testing using independently controllable voltage islands A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island s... | 09/23/2008 |
| 7427550 | Methods of fabricating passive element without planarizing Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarizati... | 09/23/2008 |
| 7426555 | Method, system, and storage medium for providing continuous communication between process equipment and an automated material handling system Exemplary embodiments of the invention include a method and system for providing continuous communication between passive equipment and active equipment. The method includes monitoring signals received from a passive equipment or active equipment. The signals relate... | 09/16/2008 |
| 7408229 | Structure and method for accurate deep trench resistance measurement A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a deep trench formed within a semiconductor substrate. The deep trench has a dielectric material formed on upper portions of sidewall surfaces thereof... | 08/05/2008 |
| 7407605 | Manufacturable CoWP metal cap process for copper interconnects An aqueous seeding solution of palladium acetate, acetic acid and chloride. ... | 08/05/2008 |
| 7406579 | Selectively changeable line width memory The invention provides for selectively changing a line width for a memory, i.e., selecting one of a plurality of line widths for a memory. The selected line width is used in communicating with one or more processors. This provides increased flexibility and efficienc... | 07/29/2008 |
| 7404874 | Method and apparatus for treating wafer edge region with toroidal plasma Method and apparatus for treating an edge region of a wafer. A toroidal shaped plasma cavity has an inner diameter which is slightly less than the diameter of the wafer being treated so that only the edge region of the wafer extends into the toroidal plasma cavity. ... | 07/29/2008 |
| 7405153 | Method for direct electroplating of copper onto a non-copper plateable layer A process for the formation of an interconnect in a semiconductor structure including the steps of forming a dielectric layer on a substrate, forming a first barrier layer on the dielectric layer, forming a second barrier layer on the first barrier layer, wherein th... | 07/29/2008 |
| 7398172 | Method and system of providing a dynamic sampling plan for integrated metrology A method and system of providing a dynamic sampling plan for integrated metrology is disclosed. The method may include modeling a sampling plan for use with a factory level advanced processing control (FL-APC) system and sending a recommended sampling plan, in respo... | 07/08/2008 |
| 7396694 | Structure for monitoring semiconductor polysilicon gate profile Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares... | 07/08/2008 |
| 7394110 | Planar vertical resistor and bond pad resistor Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In ... | 07/01/2008 |
| 7394539 | Method and apparatus for improved ellipsometric measurement of ultrathin films A method for implementing ellipsometry for an ultrathin film includes directing a polarized light beam incident upon a sample surface, receiving an initial reflected beam from the sample surface and redirecting the initial reflected beam back upon said sample surfac... | 07/01/2008 |
| 7390615 | Integrated circuit fuse and method of opening An integrated circuit, a fuse therefor and fuse opening method are disclosed. The method implements fuse opening using a wet etchant. As a result, there is no explosion that causes damage to surrounding material. In addition, use of the wet etchant allows positionin... | 06/24/2008 |
| 7388277 | Chip and wafer integration process using vertical connections A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrat... | 06/17/2008 |
