Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 7924184 | High-speed serial interface circuitry for programmable integrated circuit devices An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and a channel of high-speed serial data signal interface (e.g., transceiver) circuitry. To facil... | 04/12/2011 |
| 7848318 | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequ... | 12/07/2010 |
| 7877721 | Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are per... | 01/25/2011 |
| 7876601 | Variable sized soft memory macros in structured cell arrays, and related methods The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may h... | 01/25/2011 |
| 7869553 | Digital phase locked loop circuitry and methods Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal.... | 01/11/2011 |
| 7869343 | Field programmable gate array architectures and methods for supporting forward error correction A field-programmable gate array (“FPGA”) or programmable logic device (“PLD”) includes relatively general-purpose PLD core circuitry and relatively specialized high-speed serial interface (“HSSI”) hard IP circuitry. To better support applications that in... | 01/11/2011 |
| 7843275 | Frequency synthesizer circuitry employing delay line Frequency synthesizer circuitry employs a delay line. A reference clock signal propagates through successive stages of the delay line, and the currents drawn by output buffers of all of the stages are added at a common node. The common node current is converted to a... | 11/30/2010 |
| 7839966 | Asynchronous data sampling using CDR receivers in lock-to-reference mode Sampling and analysis of input data is implemented within the programmable logic resource without using external equipment. CDR circuitry can be set to reference clock mode. In this mode, a reference clock signal is multiplied by a factor to generate a sample rate. ... | 11/23/2010 |
| 7812659 | Clock signal circuitry for multi-channel data signaling A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and ... | 10/12/2010 |
| 7812634 | Programmable logic device transceiver architectures that facilitate using various numbers of transceiver channels together Transceiver circuitry on a programmable logic device integrated circuit (“PLD”) is preferably provided in a plurality of identical or at least similar modules. Each module preferably includes a plurality of transceiver channels and a clock source unit. Clock dis... | 10/12/2010 |
| 7804892 | Circuitry for providing programmable decision feedback equalization Equalization circuitry may be implemented by cascading a plurality of equalization stages. Each equalization stage may compensate for some of the attenuation of a received data signal. Each equalization stage may also be configured to perform decision feedback equal... | 09/28/2010 |
| 7804325 | Dedicated function block interfacing with general purpose function blocks on integrated circuits To improve interfacing between a block of dedicated function circuitry and blocks of more general purpose circuitry on an integrated circuit (“IC”), signals that are to be output by the dedicated function block are routed internally in that block so that they go... | 09/28/2010 |
| 7782935 | Half-rate DFE with duplicate path for high data-rate operation Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at ... | 08/24/2010 |
| 7779536 | Apparatus for wire coil lead placement in machinery for producing dynamo electric machine components Apparatus for forming wire coil leads that depart from wire coils inserted into a dynamo-electric machine component is provided. A plurality of wire coils may be received on an insertion tool. A wire lead may be anchored at a location on the insertion tool. A wire c... | 08/24/2010 |
| 7773668 | Adaptive equalization methods and apparatus for programmable logic devices A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fracti... | 08/10/2010 |
| 7768819 | Variable sized soft memory macros in structured cell arrays, and related methods The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may h... | 08/03/2010 |
| 7759972 | Integrated circuit architectures with heterogeneous high-speed serial interface circuitry An integrated circuit device such as a programmable logic device (“PLD”) includes a plurality of blocks of legacy circuitry. These legacy blocks leave at least one corner of the device unoccupied by such legacy circuitry. This at least one corner is used for rel... | 07/20/2010 |
| 7743496 | Cable termination methods A termination for a multi-conductor cable is made by providing a metal structure that includes a plurality of parallel but spaced apart fingers that are joined together by a connecting member adjacent at least one end of each finger. Each of the conductors in the ca... | 06/29/2010 |
| 7743288 | Built-in at-speed bit error ratio tester A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (... | 06/22/2010 |
| 7728674 | Voltage-controlled oscillator methods and apparatus Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of ... | 06/01/2010 |
| 7724031 | Staggered logic array block architecture A staggered logic array block (LAB) architecture can be provided. An integrated circuit (IC) device can include a first group of LABs substantially aligned with each other, and a second group of LABs substantially aligned with each other and coupled to the first gro... | 05/25/2010 |
| 7716623 | Programmable logic device architectures and methods for implementing logic in those architectures A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LA... | 05/11/2010 |
| 7702011 | High-speed serial data receiver architecture Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation... | 04/20/2010 |
| 7696781 | Methods and apparatus for control and configuration of programmable logic devices Circuitry and methods are provided for control and configuration of a PLD. An embodiment of the invention comprises hard IP circuitry embedded in the PLD. The circuitry may include a gigabit MAC, a hard processor, and a DMA engine. The invention permits a variety of... | 04/13/2010 |
| 7695427 | Methods and apparatus for treating body tissue sphincters and the like A plurality of structures that resiliently attract one another are provided for implanting in a patient around a body tissue structure of the patient. For example, the body tissue structure may be the esophagus, and the plurality of structures may be implanted in an... | 04/13/2010 |
| 7693691 | Systems and methods for simulating link performance Systems and methods for accurately and quickly simulating link performance of a transceiver operating with any given transmission medium are provided. Accurate and quick link simulations may be provided using a link simulation platform. The link simulation platform ... | 04/06/2010 |
| 7688106 | High-speed serial interface circuitry for programmable logic device integrated circuits High-speed serial interface (“HSSI”) transceiver circuitry (e.g., on a programmable logic device (“PLD”) integrated circuit) includes input buffer circuitry with adaptive equalization capability. The transceiver circuitry also includes an output driver, whic... | 03/30/2010 |
| 7660841 | Flexible accumulator in digital signal processing circuitry A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cy... | 02/09/2010 |
| 7659838 | Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any freque... | 02/09/2010 |
| 7659745 | Variable external interface circuitry on programmable logic device integrated circuits A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal ... | 02/09/2010 |
| 7656191 | Distributed memory in field-programmable gate array integrated circuit devices Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data pa... | 02/02/2010 |
| 7656187 | Multi-channel communication circuitry for programmable logic device integrated circuits and the like An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so tha... | 02/02/2010 |
| 7633015 | Conforming, electro-magnetic interference reducing cover for circuit components An electronic circuit component is provided with shielding for electro-magnetic interference (“EMI”) by covering at least part of the component with a layer of electrical insulation that conforms to the shape of the surface to which the insulation is applied. At... | 12/15/2009 |
| 7623609 | Dynamic phase alignment methods and apparatus Dynamic phase alignment circuitry selects from among several, phase-distributed, candidate clock signals the one of those signals that is currently best for use in controlling the timing of sampling of a serial data signal to recover the data from that signal. The c... | 11/24/2009 |
| 7622952 | Periphery clock signal distribution circuitry for structured ASIC devices A structured ASIC device includes highly flexible clock signal routing to peripheral IO circuitry of the device. A plurality of peripheral IO circuits are divided into subpluralities of adjacent ones of those circuits. Each subplurality has associated clock signal r... | 11/24/2009 |
| 7619443 | Programmable logic device architectures and methods for implementing logic in those architectures A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LA... | 11/17/2009 |
| 7602212 | Flexible high-speed serial interface architectures for programmable integrated circuit devices An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes high-speed serial data signal interface channels, some of which include more circuitry that is dedicated to performing ... | 10/13/2009 |
| 7598779 | Dual-mode LVDS/CML transmitter methods and apparatus A dual-mode LVDS/CML transmitter allows a single circuit to operate as either an LVDS transmitter or a CML transmitter. The transmitter mode can be switched by activating or deactivating appropriate circuit elements, and changing the voltage or current produced by a... | 10/06/2009 |
| 7598767 | Multi-standard data communication interface circuitry for programmable logic devices A programmable logic device includes a hard IP portion, which includes circuitry that is dedicated to receiving a high-speed serial data signal and performing certain basic functions related to byte alignment on that data signal, and a more general-purpose programma... | 10/06/2009 |
| 7589555 | Variable sized soft memory macros in structured cell arrays, and related methods The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may h... | 09/15/2009 |
