Quotables
"For a list of all the ways technology has failed to improve the quality of life, please press three."
Alice Kahn
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7602265 | Apparatus for accurate and efficient quality and reliability evaluation of micro electromechanical systems The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and low... | 10/13/2009 |
| 7305320 | Metrology tool recipe validator using best known methods A method of preparing recipes for operating a metrology tool, each recipe including a set of instructions for measuring dimensions in a microelectronic feature. A database includes a plurality of known instructions with best known methods for measuring different fea... | 12/04/2007 |
| 7190042 | Self-aligned STI for narrow trenches A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the tren... | 03/13/2007 |
| 6933191 | Two-mask process for metal-insulator-metal capacitors and single mask process for thin film resistors MIM capacitors and thin film resistors are fabricated with at least one less lithographic step than the prior art methods. The process step reduction is realized by using semi-transparent metallic electrodes, fabricated with a two-mask process, which provides for di... | 08/23/2005 |
| 6884641 | Site-specific methodology for localization and analyzing junction defects in mosfet devices This invention relates to a method for electrically localizing site-specific defective sub 130 nm node MOSFET devices with shallow (less than 80 nm deep) source/drain junctions utilizing bulk silicon, or Silicon on Insulator (SOI), or strained silicon (SE), followed... | 04/26/2005 |
| 6852629 | Backside integrated circuit die surface finishing technique and tool A method for preparing a semiconductor die for analysis comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, prov... | 02/08/2005 |
