Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 8160186 | Variable bandwidth automatic gain control Provided is automatic gain control (AGC) in which a feedback filter has a parameter that is changed based on information regarding data-packet boundaries. In one representative embodiment, the bandwidth of the filter temporarily is increased, or the time constant of... | 04/17/2012 |
| 8132023 | Apparatus and method for performing transparent hash functions A method for performing hash operations including: receiving a hash instruction that prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality... | 03/06/2012 |
| 8132022 | Apparatus and method for employing configurable hash algorithms A method for performing hash operations including: receiving a hash instruction that is part of an application program, where the hash instruction prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into ... | 03/06/2012 |
| 8102843 | Switching apparatus and method for providing shared I/O within a load-store fabric An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of oper... | 01/24/2012 |
| 8085062 | Configurable bus termination for multi-core/multi-package processor configurations A multi-core/multi-package bus termination apparatus includes a configuration array and a plurality of drivers. The configuration array generates location/protocol signals that each direct one of the plurality of drivers on the bus to employ location-based bus termi... | 12/27/2011 |
| 8060755 | Apparatus and method for providing user-generated key schedule in a microprocessor cryptographic engine An apparatus and method for performing cryptographic operations within microprocessor. The apparatus includes an instruction register having a cryptographic instruction disposed therein, a keygen unit, and an execution unit. The cryptographic instruction is received... | 11/15/2011 |
| 7953074 | Apparatus and method for port polarity initialization in a shared I/O device An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus includes a first plurality of I/O ports, a second I/O port, and a plurality of port initialization logic elements. The first plurality of... | 05/31/2011 |
| 7925891 | Apparatus and method for employing cryptographic functions to generate a message digest The present invention provides an apparatus and method for performing cryptographic operations on a plurality of message blocks within a processor to generate a message digest. In one embodiment, the apparatus has an x86-compatible microprocessor that includes trans... | 04/12/2011 |
| 7921300 | Apparatus and method for secure hash algorithm An x86-compatible microprocessor that executes an application program fetched from memory, including a single, atomic hash instruction directing the x86-compatible microprocessor to perform the hash operation. The single, atomic hash instruction has an opcode field ... | 04/05/2011 |
| 7917658 | Switching apparatus and method for link initialization in a shared I/O environment An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality of I/O ports is coupled to a pluralit... | 03/29/2011 |
| 7900129 | Encoded mechanism for source synchronous strobe lockout An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed ve... | 03/01/2011 |
| 7900080 | Receiver mechanism for source synchronous strobe lockout An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The se... | 03/01/2011 |
| 7900055 | Microprocessor apparatus and method for employing configurable block cipher cryptographic algorithms An apparatus for performing cryptographic operations. The apparatus includes an x86-compatible microprocessor that has fetch logic, algorithm logic, and execution logic. The fetch logic is configured to receive a single, atomic cryptographic instruction as one of th... | 03/01/2011 |
| 7899143 | Adjustment mechanism for source synchronous strobe lockout An apparatus for adjusting a lockout time in a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock and generates adjusted and encoded vectors, both indicating a first time period. A select vector ... | 03/01/2011 |
| 7844053 | Microprocessor apparatus and method for performing block cipher cryptographic functions A microprocessor apparatus is provided, for performing a cryptographic operation. The microprocessor apparatus includes an x86-compatible microprocessor that has fetch logic, a cryptography unit, and an integer unit. The fetch logic is configured to fetch an applica... | 11/30/2010 |
| 7843225 | Protocol-based bus termination for multi-core processors A multi-core bus termination apparatus includes a protocol analyzer and a plurality of drivers. The protocol analyzer is disposed within a processor core and configured to receive one or more protocol signals, and is configured to indicate whether or not the process... | 11/30/2010 |
| 7836211 | Shared input/output load-store architecture An apparatus and method are provided that enable I/O devices to be shared and/or partitioned among a plurality of operating system domains within the load-store fabric of each of the operating system domains without requiring modification to the operating system or ... | 11/16/2010 |
| 7804923 | Apparatus and method for locking out a source synchronous strobe receiver An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The se... | 09/28/2010 |
| 7788433 | Microprocessor apparatus providing for secure interrupts and exceptions An apparatus for executing secure code, having a microprocessor coupled to a secure non-volatile memory via a private bus a system memory via a system bus. The microprocessor executes non-secure application programs and a secure application program. The microprocess... | 08/31/2010 |
| 7767492 | Location-based bus termination for multi-core/multi-package processor configurations A multi-core/multi-package bus termination apparatus includes a first node, a location array, and a plurality of drivers. The first node receives a signal indicating whether a package upon which the processor core is disposed is internal to the bus or at a far end o... | 08/03/2010 |
| 7698483 | Switching apparatus and method for link initialization in a shared I/O environment An apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality is configured to route transactions betwee... | 04/13/2010 |
| 7668988 | Data bus inversion detection mechanism A bus inversion apparatus includes exclusive-OR gates and an inversion detector. The exclusive-OR gates are coupled to an instant data bus and a last data bus. The data buses have a corresponding plurality of bits, where the exclusive-OR gates perform a bitwise comp... | 02/23/2010 |
| 7664810 | Microprocessor apparatus and method for modular exponentiation A technique is provided for performing modular multiplication. In one embodiment, an apparatus in a microprocessor is provided for accomplishing modular multiplication operations. The apparatus includes translation logic and execution logic. The translation logic re... | 02/16/2010 |
| 7647479 | Non-temporal memory reference control mechanism An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extende... | 01/12/2010 |
| 7647478 | Suppression of store checking An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruc... | 01/12/2010 |
| 7590787 | Apparatus and method for ordering transaction beats in a data transfer A microprocessor including a cache memory and bus interface logic. The bus interface logic is interfaced with request signals and data signals and includes a request interface and a response interface. The request interface provides a request via the request signals... | 09/15/2009 |
| 7546446 | Selective interrupt suppression An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of interrupts at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an ... | 06/09/2009 |
| 7543134 | Apparatus and method for extending a microprocessor instruction set An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended in... | 06/02/2009 |
| 7543094 | Target readiness protocol for contiguous write A method of performing contiguous write transactions on a processor bus according to an embodiment of the present invention includes detecting, by a bus agent, a request for a write cycle, asserting, by the bus agent, a target ready signal for one clock cycle in res... | 06/02/2009 |
| 7543090 | Double-pumped/quad-pumped variation mechanism for source synchronous strobe lockout An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed ve... | 06/02/2009 |
| 7542566 | Apparatus and method for performing transparent cipher block chaining mode cryptographic functions An apparatus and method for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction, CBC block pointer logic, and execution logic. The cryptographic instruction is received by a pipeline microprocessor as part of an applic... | 06/02/2009 |
| 7539876 | Apparatus and method for generating a cryptographic key schedule in a microprocessor An apparatus and method for performing cryptographic operations. In one embodiment, an apparatus is provided for performing cryptographic operations. The apparatus includes fetch logic, keygen logic, and execution logic. The fetch logic is disposed within a micropro... | 05/26/2009 |
| 7536560 | Microprocessor apparatus and method for providing configurable cryptographic key size The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a microprocessor, where the size cryptographic key that is employed is programmable. In one embodiment, an apparatus for perform... | 05/19/2009 |
| 7532722 | Apparatus and method for performing transparent block cipher cryptographic functions The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a crypt... | 05/12/2009 |
| 7529912 | Apparatus and method for instruction-level specification of floating point format Apparatus and method are provided for extending a microprocessor instruction set to allow for instruction-level specification of floating point format to be employed during execution of an associated floating point operation. The apparatus includes translation logic... | 05/05/2009 |
| 7529368 | Apparatus and method for performing transparent output feedback mode cryptographic functions An apparatus and method for performing cryptographic operations on a plurality of input data blocks. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction, OFB mode logic, and executio... | 05/05/2009 |
| 7529367 | Apparatus and method for performing transparent cipher feedback mode cryptographic functions An apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction, CFB mode ... | 05/05/2009 |
| 7519833 | Microprocessor apparatus and method for enabling configurable data block size in a cryptographic engine The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor, where the size of the input data blocks is programmable. In one embodiment, an apparatus for performing cryptograph... | 04/14/2009 |
| 7514966 | Fast, low offset ground sensing comparator A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small ... | 04/07/2009 |
| 7502943 | Microprocessor apparatus and method for providing configurable cryptographic block cipher round results The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes fetch l... | 03/10/2009 |
