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| Number | Title | Issue Date |
| 8179178 | Registers with reduced voltage clocks A register circuit including a level shift circuit, a latch isolation circuit, and a keeper circuit for registering data with a lower voltage clock signal. The level shift circuit switches a level shift node between a reference voltage level and an upper voltage lev... | 05/15/2012 |
| 8178886 | Multi-layered LED epitaxial structure with light emitting unit A method for manufacturing a semiconductor light emitting device includes: (a) providing a temporary substrate; (b) forming a multi-layered LED epitaxial structure, having at least one light emitting unit, on the temporary substrate, wherein a first surface of the l... | 05/15/2012 |
| 8176347 | Microprocessor that performs adaptive power throttling A microprocessor that performs adaptive power throttling includes a calculation unit configured to calculate an average power consumed by the microprocessor over a most recent predetermined sample time and to determine whether the average power is less than a predet... | 05/08/2012 |
| 8171271 | Server device and method of sharing basic input/output system A server device and a method of sharing a basic input/output system (BIOS) include a plurality of mainboards, a circuit board, and a memory unit, and a switching unit disposed on the circuit board. A single memory unit stores a plurality of BIOS entity program segme... | 05/01/2012 |
| 8161246 | Prefetching of next physically sequential cache line after cache line that includes loaded page table entry A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that includes an indicator that the load request is loading a page table entry. The prefetch unit is configure... | 04/17/2012 |
| 8160186 | Variable bandwidth automatic gain control Provided is automatic gain control (AGC) in which a feedback filter has a parameter that is changed based on information regarding data-packet boundaries. In one representative embodiment, the bandwidth of the filter temporarily is increased, or the time constant of... | 04/17/2012 |
| 8145890 | Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user program includes a conditional branch instruction. A first fetch unit fe... | 03/27/2012 |
| 8137106 | Method for improving spelling and sensitivity to letter-sound correspondences using spelling patterns and word families on a computing device Methodologies for improving a student's phonemic awareness, decoding, spelling, oral and written comprehension are described herein. The method is embodied in a suite of twelve exercises operable on a computing device. The exercises are geared towards training of 1s... | 03/20/2012 |
| 8135970 | Microprocessor that performs adaptive power throttling A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined ma... | 03/13/2012 |
| 8132023 | Apparatus and method for performing transparent hash functions A method for performing hash operations including: receiving a hash instruction that prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality... | 03/06/2012 |
| 8132022 | Apparatus and method for employing configurable hash algorithms A method for performing hash operations including: receiving a hash instruction that is part of an application program, where the hash instruction prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into ... | 03/06/2012 |
| 8131984 | Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in th... | 03/06/2012 |
| 8117432 | Method for controlling boot sequence of server A method for controlling a boot sequence of a server includes the following steps. A boot image is created, and a first proxy server program is placed into the boot image. The first proxy server program communicates with a management server. The boot image is restor... | 02/14/2012 |
| 8116466 | Apparatus and method for testing sound input and output of sound card An apparatus and a method for testing a sound card are applicable for detecting whether a sound leakage problem occurs to a sounding interface of the sound card. The testing apparatus includes a switching circuit and a switching unit. The switching circuit is electr... | 02/14/2012 |
| 8108624 | Data cache with modified bit array A microprocessor includes first and second functional units and a data cache having a data array having a write port, a modified bit array having a read port and a write port, and a tag array having a read port, each array having the corresponding predetermined orga... | 01/31/2012 |
| 8103267 | Femtocell base station with mobile station capability A communication device that includes a femtocell base station and a mobile station transmitter/receiver. The femtocell base station may provide bidirectional internet protocol (IP) communication for one or mobile devices to a cellular network. The femtocell base sta... | 01/24/2012 |
| 8102843 | Switching apparatus and method for providing shared I/O within a load-store fabric An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of oper... | 01/24/2012 |
| 8094467 | Induction power system An induction power system configured to drive a load includes a primary side circuit (PSC) and a secondary side circuit (SSC). The PSC has a main inductor configured to generate a current-induced magnetic field. The SSC has an induction electrification unit (IEU) an... | 01/10/2012 |
| 8090931 | Microprocessor with fused store address/store data microinstruction A microprocessor includes an instruction translator that translates PUSHF, POP, and MOVSB x86 macroinstructions into multiple microinstructions that include a fused store microinstruction. For PUSHF, first and second microinstructions moves the x86 EFLAGS register i... | 01/03/2012 |
| 8085062 | Configurable bus termination for multi-core/multi-package processor configurations A multi-core/multi-package bus termination apparatus includes a configuration array and a plurality of drivers. The configuration array generates location/protocol signals that each direct one of the plurality of drivers on the bus to employ location-based bus termi... | 12/27/2011 |
| 8083523 | Method for developing cognitive skills using spelling and word building on a computing device Methodologies for improving a student's phonemic awareness, decoding, spelling, oral and written comprehension are described herein. The method is embodied in a suite of twelve exercises operable on a computing device. The exercises are geared towards training of 1s... | 12/27/2011 |
| 8081591 | Access terminal paging improvements A method, apparatus, and system are disclosed providing improved paging procedures in a wireless communication system. In one embodiment, a Power-down Registration signal is transmitted via a 1×RTT modem from an Access Terminal (AT) to an Access Network (AN) in a w... | 12/20/2011 |
| 8074060 | Out-of-order execution microprocessor that selectively initiates instruction retirement early A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instru... | 12/06/2011 |
| 8069340 | Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions A microprocessor instruction translator translates a macroinstruction into three microinstructions to perform a read/modify/write operation on a memory operand. A first microinstruction instructs the microprocessor to calculate a source address and to load the memor... | 11/29/2011 |
| 8069339 | Microprocessor with microinstruction-specifiable non-architectural condition code flag register A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plur... | 11/29/2011 |
| 8060755 | Apparatus and method for providing user-generated key schedule in a microprocessor cryptographic engine An apparatus and method for performing cryptographic operations within microprocessor. The apparatus includes an instruction register having a cryptographic instruction disposed therein, a keygen unit, and an execution unit. The cryptographic instruction is received... | 11/15/2011 |
| 8059592 | Access terminal which handles multiple user connections System and method for handling multiple connection requests between an Access Terminal (AT) and an Access Network (AN). The method may include receiving a first connection request. Connection request information regarding a number of connection requests may be updat... | 11/15/2011 |
| 8059426 | Electrostatic guiding device achieved by using metal sputtering and plastic case An electrostatic discharge guide using metal sputtering process and modifying plastic case is applied to an electronic device. The plastic case and a metal case are laminated. The plastic case is defined with a tip portion spaced from the metal case on side wall the... | 11/15/2011 |
| 8059098 | Electronic device with automatic switching input interfaces and switching method thereof An electronic device with automatic switching input interfaces and a switching method thereof. The electronic device supports an Advanced Configuration Power Interface (ACPI), and includes a display unit, a storage unit, a memory unit, and an embedded controller. Th... | 11/15/2011 |
| 8051190 | Nak message transmission with quicknak indication System and method for processing received packets. A QuickNak (QN) packet may be received. The QN packet may include a segmentation and reassembly (SAR) packet. The SAR packet may be delivered to a SAR receiver and it may be determined if there are missing packets, ... | 11/01/2011 |
| 8051116 | Apparatus and method for generating packed sum of absolute differences A method for executing an MMX PSADBW instruction by a microprocessor. The method includes generating packed differences of packed operands of the instruction and generating borrow bits associated with each of the packed differences; for each of the packed difference... | 11/01/2011 |
| 8046400 | Apparatus and method for optimizing the performance of x87 floating point addition instructions in a microprocessor A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and generates a sum from its addends. The FPU determines whether any condition... | 10/25/2011 |
| D647226 | LED lamp | 10/18/2011 |
| 8032684 | Programmable bridge header structures A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. Th... | 10/04/2011 |
| 8032659 | Method and apparatus for a shared I/O network interface controller A network interface controller is provided which is shareable by a plurality of operating system domains (OSDs) within their load-store architecture. The controller includes local resources for corresponding to the OSDs, and global resources corresponding to both th... | 10/04/2011 |
| 8024644 | Communication signal decoding Provided are systems, methods and techniques that use an embedded error-detection code within a received communication signal to determine when to stop iterative decoding of the communication signal. ... | 09/20/2011 |
| 8013649 | Dynamic clock feedback latch A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first t... | 09/06/2011 |
| 8006014 | PCI-Express data link transmitter employing a plurality of dynamically selectable data transmission priority rules A PCI-Express data link transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one of multiple scheduled TLPs and DLLPs based on their distinct types. A selector selects one of the arbiters to select the one of the multiple s... | 08/23/2011 |
| 8000111 | Electronic device structure An electronic device structure includes an upper case, a lower case, a main board, a suspending member, and a fixing member. The upper case and the lower case respectively have an upper combining column and a lower combining column. The main board has a through hole... | 08/16/2011 |
| 7996650 | Microprocessor that performs speculative tablewalks A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory whose physical address speci... | 08/09/2011 |
