Horizon IP Pte Ltd - US Patent Attorneys and Agents

Attorney: Horizon IP Pte Ltd

Number of patents: 104
Last date: May 10, 2011

Number	Title	Issue Date
7939413	Embedded stressor structure and process An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example...	05/10/2011
7939348	E-beam inspection structure for leakage analysis A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined str...	05/10/2011
7935632	Reduced metal pipe formation in metal silicide contacts Formation of metal pipes resulting from formation of metal silicide contacts are reduced or avoided. To reduce formation of metal pipes, an epitaxial layer is formed over the diffusion region on which the metal silicide contact is formed. The epitaxial layer reduces...	05/03/2011
7935589	Enhanced stress for transistors A transistor disposed on a substrate includes a gate, spacers on gate sidewalls, and diffusion regions adjacent to the gate. Silicide contacts on the diffusion regions are displaced from the spacers by a distance G. Stressors may be provided in the diffusion region ...	05/03/2011
7932152	Method of forming a gate stack structure A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the ...	04/26/2011
7930053	Virtual platform to facilitate automated production A method of automating validation in a manufacturing facility is disclosed. The method comprises defining requirements, selecting and integrating automated devices for manufacturing. A hub-box with communication links is used to integrate the automated devices. The ...	04/19/2011
7923180	Cross technology reticles A method of fabricating a device is presented. The method includes forming a mask that includes multiple images. A substrate is patterned using the mask. An image of the multiple images corresponds to a respective patterning process. The substrate is processed furth...	04/12/2011
7902066	Damascene contact structure for integrated circuits Interconnects for integrated circuits, such as damascene structures are formed using a hard mask. The hard mask is formed from, for example, high-k dielectric material such as hafnium oxide or other materials having high etch selectivity to the interconnect dielectr...	03/08/2011
7898742	Variable focus microlens A microlens chip comprises a variable focus fluidic microlens and actuator. The actuator varies the pressure in a fluidic channel in the microlens chip which is coupled to an aperture opening containing the microlens. Applying an electric field to the actuator creat...	03/01/2011
7888752	Structure and method to form source and drain regions over doped depletion regions A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive ty...	02/15/2011
7888214	Selective stress relaxation of contact etch stop layer through layout design A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the ...	02/15/2011
7846805	Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained diff...	12/07/2010
7846800	Avoiding plasma charging in integrated circuits A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit...	12/07/2010
7879673	Patterning nanocrystal layers A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with first and second regions with a first device layer. A second device layer including nanocrystals is also formed. A cover layer is provided over the seco...	02/01/2011
7867862	Semiconductor structure including high voltage device A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the sub...	01/11/2011
7863141	Integration for buried epitaxial stressor Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a stressor layer over the substrate. We form a strained layer over the str...	01/04/2011
7855143	Interconnect capping layer and method of fabrication The present invention relates to an interconnect capping layer and a method of fabricating a capping layer for an interconnect. In particular, but not exclusively, the invention relates to a capping layer for a copper interconnect used to interconnect elements in an...	12/21/2010
7843673	Antenna diodes with electrical overstress (EOS) protection An antenna diode circuit for discharging static charge accumulated during wafer processing is described. The antenna diode circuit includes first and second junctions coupled to a circuit element and substrate. Between the first and second junctions is a diode circu...	11/30/2010
7833900	Interconnections for integrated circuits including reducing an overburden and annealing The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of...	11/16/2010
7829422	Integrated circuit having ultralow-K dielectric layer A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect t...	11/09/2010
7825750	EMI filter for controlling cutoff frequency Disclosed relates to an electromagnetic interference (EMI) filter. Capacitance and resistance or inductance of an EMI filter, which includes a resistor and a capacitor or an inductor and a capacitor, can be controlled, such that a cutoff frequency can be freely cont...	11/02/2010
7824968	LDMOS using a combination of enhanced dielectric stress layer and dummy gates First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Secon...	11/02/2010
7790617	Formation of metal silicide layer over copper interconnect for reliability enhancement A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We ...	09/07/2010
7776699	Strained channel transistor structure and method A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material differe...	08/17/2010
7767577	Nested and isolated transistors with reduced impedance difference A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, R	08/03/2010
7745320	Method for reducing silicide defects in integrated circuits A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the...	06/29/2010
7741187	Lateral junction varactor with large tuning range Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and...	06/22/2010
7727856	Selective STI stress relaxation through ion implantation A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer havi...	06/01/2010
7718500	Formation of raised source/drain structures in NFET with embedded SiGe in PFET A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE re...	05/18/2010
7710182	Reliable level shifter of ultra-high voltage device used in low power application The present invention relates to integrated circuits. In particular, it relates to an IC comprising a receiving stage for receiving an input signal, an output stage for generating an output signal having a larger voltage range than the input signal and a level shift...	05/04/2010
7678586	Structure and method to prevent charge damage from e-beam curing process An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anod...	03/16/2010
7674562	Angled-wedge chrome-face wall for intensity balance of alternating phase shift mask A method for forming a phase shift mask is presented. The method includes providing a substrate including a transparent material having first, second and third regions, the third region being disposed between the first and second regions. The method also includes fo...	03/09/2010
7672748	Automated manufacturing systems and methods An efficient manufacturing automation system and method is described. The system and method include bays, with each bay having a group of tools. Temporary storage locations are provided. A transport system facilitates movement of materials from the tools. The system...	03/02/2010
7670946	Methods to eliminate contact plug sidewall slit A method to form a barrier layer and contact plug using a touch up RIE. In a first embodiment, we form a first barrier layer over the dielectric layer and the substrate in the contact hole. The first barrier layer is comprised of Ta. A second barrier layer is formed...	03/02/2010
7659174	Method to enhance device performance with selective stress relief A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over ...	02/09/2010
7655388	Mask and method to pattern chromeless phase lithography contact hole A chromeless phase shift mask and Method for making and using. The A chromeless phase shift mask is used to pattern contact holes. The chromeless phase shift mask preferably comprises: a first phase shift region and a second phase shift region; the first region is c...	02/02/2010
7652355	Integrated circuit shield structure Embodiments of the invention provide an integrated circuit structure comprising: a substrate; a shield structure comprising a shield member and a ground strap formed on the substrate, wherein the shield member comprises a non-metallic portion, and the ground strap c...	01/26/2010
7645687	Method to fabricate variable work function gates for FUSI devices An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over t...	01/12/2010
7618873	MOS varactors with large tuning range A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the dep...	11/17/2009
7615433	Double anneal with improved reliability for dual contact etch stop liner scheme A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and...	11/10/2009

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Attorney: Horizon IP Pte Ltd