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| Number | Title | Issue Date |
| 6435398 | Method for chemically reworking metal layers on integrated circuit bond pads A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads covered by deposited layers of a barrier metal and a bondable metal. After identifying the wafers with off-spec metal layers, the wafers are chemically etched using s... | 08/20/2002 |
| 6432749 | Method of fabricating flip chip IC packages with heat spreaders in strip format Methods for fabricating plastic molded thermally enhanced flip chip packages in which the heat spreaders are assembled in strip format is disclosed, including the first step of providing the heat spreader strip. Inclusion of heat spreaders in strip format... | 08/13/2002 |
| 6432744 | Wafer-scale assembly of chip-size packages A wafer-scale assembly apparatus for integrated circuits and method for forming the wafer-scale assembly. A semiconductor wafer including a plurality of circuits is provided with a plurality of metal contact pads as electrical entry and exit ports. A firs... | 08/13/2002 |
| 6424027 | Low pass filter integral with semiconductor package A semiconductor package substrate for assembling an integrated circuit chip operable at fast ramp rate signals and clock rates, comprising an insulating support having a region for attaching said chip; a pattern of electrical interconnections, disposed on... | 07/23/2002 |
| 6413150 | Dual dicing saw blade assembly and process for separating devices arrayed a substrate A dicing saw blade assembly with parallel blades separated by a spacer and attached to a single spindle on an automated dicing saw, is applicable to precisely separating CSP or MCM devices which have been fabricated on a polymeric substrate. Two parallel ... | 07/02/2002 |
| 6396136 | Ball grid package with multiple power/ground planes A package for a flip chip integrated circuit including an interposer with electrical interconnecting for signal, power, and ground contacts. Routing is accomplished on only two conductor layers through the use of selective planes and buses. Multiple power... | 05/28/2002 |
| 6392263 | Integrated structure for reduced leakage and improved fill-factor in CMOS pixel A densely integrated pixel, fabricated by CMOS technology, comprises a photodiode formed by a n-well, with cathode, surrounded by a p-well; a reset MOS transistor formed such that its polysilicon gate is positioned, for diode control, across the junction ... | 05/21/2002 |
| 6388336 | Multichip semiconductor assembly A multichip semiconductor assembly comprising a semiconductor chip stack comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads; a leadframe for interconnecting semicon... | 05/14/2002 |
| 6384486 | Bonding over integrated circuits An architecture and method of fabrication for an integrated circuit 200 having a bond pad 208; at least one portion of said integrated circuit disposed under said contact pad and electrically connected to said pad through a via 205; a combination of a bon... | 05/07/2002 |
| 6377061 | Expanded lead pitch for semiconductor package and method of electrical testing The invention relates to packages of semiconductor devices, specifically of the surface mount and Quad Flat Pack families, that can be used in current semiconductor device production, and to a method of automated testing. The packages have a plurality of ... | 04/23/2002 |
| 6376901 | Palladium-spot leadframes for solder plated semiconductor devices and method of fabrication A leadframe for use with integrated circuit chips Comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding w... | 04/23/2002 |
| 6373127 | Integrated capacitor on the back of a chip A semiconductor device is disclosed. The device includes an integrated circuit chip having integral de-coupling capacitors on the chip backside. The de-coupling capacitors includes a metal layer in intimate contact with the semiconductor substrate of the ... | 04/16/2002 |
| 6372623 | Semiconductor device and method of fabrication A process for the fabrication of an integrated circuit assembly, using thin film platinum metallization to provide edge-side contacts suitable for solder ball connections. Three-dimensional laser ablation may be used for patterning metal films. A multi-ch... | 04/16/2002 |
| 6365980 | Thermally enhanced semiconductor ball grid array device and method of fabrication A semiconductor device comprising a thermally conductive foil including a chip mount portion having first and second surfaces; an integrated circuit chip attached to said first surface; a body of encapsulation material molded around said chip and said fir... | 04/02/2002 |
| 6365978 | Electrical redundancy for improved mechanical reliability in ball grid array packages A packaged semiconductor device with electrical redundancy for improved mechanical reliability and a method for fabrication are disclosed. The device comprises a semiconductor chip having an integrated circuit, said circuit having a multitude of electrica... | 04/02/2002 |
| 6365976 | Integrated circuit device with depressions for receiving solder balls and method of fabrication A semiconductor device, especially a Ball Grid Array or Chip Scale Package, comprising an integrated circuit chip having at least one input/output terminal; a body of encapsulation material molded around said chip, forming a generally flat surface includi... | 04/02/2002 |
| 6365974 | Flex circuit substrate for an integrated circuit package A double sided electrical connection flexible circuit particularly useful as a substrate for an area array integrated package, and the method of fabricating the structure is described. A circuit having interconnections on one surface and solder ball conta... | 04/02/2002 |
| 6365958 | Sacrificial structures for arresting insulator cracks in semiconductor devices A semiconductor wafer is disclosed comprising a substrate having a surface carrying an array of integrated circuit chips bordered by dicing lines; at least two sets of substantially parallel structures within each of said dicing lines, each set extending ... | 04/02/2002 |
| 6363293 | Video wire bonded system and method of operation A video wire bonder system includes a processor (12) coupled to an imaging station (14), an input device (16), a display (18), and a memory (20). Processor (12) generates an image overlay (30) having a graphical representation of each video wire bond betw... | 03/26/2002 |
| 6348719 | Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second dop... | 02/19/2002 |
| 6339254 | Stacked flip-chip integrated circuit assemblage A stacked multichip assemblage including a plurality of integrated circuit die directly attached to a substrate having pads corresponding to terminals on the die, and interconnections between the die, and also to external contacts. The stacked integrated ... | 01/15/2002 |
| 6338973 | Semiconductor device and method of fabrication A mass production process for semiconductor circuits and modules using a combination of thin film platinum metallization dielectric masking, and three-dimensional laser ablation, in conjunction with a solder combinations and melting temperatures. These co... | 01/15/2002 |
| 6337445 | Composite connection structure and method of manufacturing A bump connection structure and a method of attachment to integrated circuits or packages is provided which comprises a prefabricated core structure coated with solderable metal layers to form a composite bump. Said composite bump is aligned to contact pa... | 01/08/2002 |
| 6331737 | Method of encapsulating thin semiconductor chip-scale packages A method of encapsulating a semiconductor device comprising the steps of providing a mold having top and bottom halves each with cavities for holding semiconductor devices, and further having gates and runners for feeding encapsulation material into said ... | 12/18/2001 |
| 6320255 | Rerouted semiconductor device and method of fabrication The invention relates to a flexible and cost-effective method for fabricating customized rerouting metallization of the circuit contact pads. Localized depositions of insulating as well as conducting paths are provided with the capability for manufacturin... | 11/20/2001 |
| 6316822 | Multichip assembly semiconductor Multichip semiconductor assembly comprising a semiconductor chip stack comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads, and a passive surface; a leadframe for in... | 11/13/2001 |
| 6303977 | Fully hermetic semiconductor chip, including sealed edge sides A structure and method for forming a hermetically sealed semiconductor chip having an active and a passive surface and four edge sides, each edge side having only a single plane; said active surface having an integrated circuit including multiple deposite... | 10/16/2001 |
| 6303407 | Method for the transfer of flux coated particles to a substrate A method for loading solder particles (14) onto an substrate comprising applying a flux (18) directly onto solder particles (14) either prior to or following adhering the solder particles (14) onto adhesive areas (30) of an adhesive coated film (20). The ... | 10/16/2001 |
| 6278616 | Modifying memory device organization in high density packages A high density memory module is disclosed comprising a first packaged integrated circuit memory device having therein a first electrically insulating carrier and a first conductive routing pattern integral with said first carrier, and at least a first sem... | 08/21/2001 |
| 6271109 | Substrate for accommodating warped semiconductor devices A substrate for solder ball assembling a semiconductor device substantially parallel onto said substrate, said device having a plurality of terminals arrayed on a warped surface, comprising an electrically insulating surface including a plurality of discr... | 08/07/2001 |
| 6268662 | Wire bonded flip-chip assembly of semiconductor devices A semiconductor assembly comprising a semiconductor chip having an active and a passive surface, said active surface including an integrated circuit and a plurality of bonding pads; said bonding pads having a metallization suitable for wire bonding; an ar... | 07/31/2001 |
| 6249963 | System and method for coupling conductive pellets to a component of an integrated circuit A system (10) for coupling conductive pellets (40) to a component (12) of an integrated circuit has a substantially planar ribbon (14) that includes a conductive material. A punching apparatus (16) and (38) penetrates the ribbon (14) to form the conductiv... | 06/26/2001 |
| 6232662 | System and method for bonding over active integrated circuits An architecture and method of fabrication for an integrated circuit having a reinforced bond pad comprising at least one portion of the integrated circuit disposed under the bond pad; and this at least one circuit portion comprises at least one dielectric... | 05/15/2001 |
| 6228680 | Low stress method and apparatus for underfilling flip-chip electronic devices A semiconductor assembly and method of fabrication comprising an integrated circuit chip, an electrically insulating substrate, a multitude of solder balls for interconnecting both parts while spacing them apart by a gap, and a polymeric encapsulant filli... | 05/08/2001 |
| 6218202 | Semiconductor device testing and burn-in methodology A packaged semiconductor device and a method for burn-in and testing are disclosed. The package comprises a carrier having a pattern of contact pads for electrical connection, and also a pattern of testing pads for electrical characterization such that th... | 04/17/2001 |
| 6213347 | Low stress method and apparatus of underfilling flip-chip electronic devices An apparatus for the fabrication of a semiconductor assembly and a method of underfilling flip-chip devices are disclosed. The apparatus for multiple controlled dispensing of polymeric precursors filled with silica and anhydrides comprises a center feed t... | 04/10/2001 |
| 6211462 | Low inductance power package for integrated circuits The invention provides a low inductance semiconductor package for RF circuits having a flat leadframe with internal leads formed upward to be in very close proximity to the die mount pad. The die mount pad is exposed through the package backside and serve... | 04/03/2001 |
| 6204094 | Method and apparatus for populating an adhesive sheet with particles A method for assembling electronic devices by moving particles (12) on an adhesive sheet (35) having a plurality of adhesive areas (30), comprising the steps of loading the particles (12) onto the adhesive sheet (35) and transferring kinetic energy from a... | 03/20/2001 |
| 6187166 | Integrated solution electroplating system and process A method and system for electroplating a metal coating onto a continuous part, such as the leadframe stock used in packaging integrated circuits, whereby the method comprises plating metal from a series of plating baths having the same or compatible chemi... | 02/13/2001 |
