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| Number | Title | Issue Date |
| 8171234 | Multi-bank multi-port architecture A memory system including a plurality of ports and a memory core having a plurality of memory banks. Access requests received at the ports are broadcast to the memory banks. Multiple memory banks may be concurrently accessed in response to access requests received o... | 05/01/2012 |
| 8139408 | Scalable electrically eraseable and programmable memory A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a secon... | 03/20/2012 |
| 8139399 | Multiple cycle memory write completion A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operati... | 03/20/2012 |
| 8093650 | Scalable electrically eraseable and programmable memory (EEPROM) cell array A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of t... | 01/10/2012 |
| 8061928 | Utilities access closure A concrete lid for an in-ground utilities box includes a plastic reinforcement structure filled with concrete. The plastic reinforcement structure includes one or more plastic sidewalls that protect the edges of the lid from damage. The upper and lower surfaces of t... | 11/22/2011 |
| 8047383 | Rackmount system including conversion rail A rackmount chassis includes removable supports that provide interior support for blades having mounting edge-to-mounting edge dimensions that are less than the full chassis width. The removable supports are mounted on parallel support plates that span the full widt... | 11/01/2011 |
| 8044724 | Low jitter large frequency tuning LC PLL for multi-speed clocking applications The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop ... | 10/25/2011 |
| 8001397 | System software for managing power allocation to Ethernet ports in the absence of mutually exclusive detection and powering cycles in hardware A method of allocating power to ports in an Ethernet switch, including: (1) determining the available capacity of a power pool used to supply the ports, (2) assigning a configuration power to each of the ports, (3) selecting a port to be enabled... | 08/16/2011 |
| 7944281 | Constant reference cell current generator for non-volatile memories A reference current generation circuit generates a first branch current that varies by a first percentage in response to variations in a first supply voltage and variations in transistor threshold voltage. The first branch current is mirrored to create a correspondi... | 05/17/2011 |
| 7920424 | Scalable electrically eraseable and programmable memory (EEPROM) cell array A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of t... | 04/05/2011 |
| 7919367 | Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventin... | 04/05/2011 |
| 7830714 | Non-volatile memory with high reliability A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cel... | 11/09/2010 |
| 7795087 | Ultra-violet protected tamper resistant embedded EEPROM A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric st... | 09/14/2010 |
| 7791975 | Scalable embedded DRAM array A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor ... | 09/07/2010 |
| 7774628 | Enabling/disabling power-over-ethernet software subsystem in response to power supply status An Ethernet switch includes 12-Volt and 48-Volt power sourcing modules, system software, Ethernet interface modules and optional power over Ethernet (PoE) modules. The Ethernet interface modules are motherboards that include the circuitry required to implement a non... | 08/10/2010 |
| 7755382 | Current limited voltage supply A current limited voltage supply including a transistor and a capacitor is provided for powering digital logic cells of an integrated circuit. The transistor is connected in a current mirror configuration, such that a constant reference current is mirrored through t... | 07/13/2010 |
| 7754564 | Method for fabricating three-dimensional control-gate architecture for single poly EPROM memory devices in planar CMOS technology A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is... | 07/13/2010 |
| 7754559 | Method for fabricating capacitor structures using the first contact metal A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided... | 07/13/2010 |
| 7748926 | Utilities access closure A concrete lid for an in-ground utilities box includes a plastic reinforcement structure filled with concrete. The plastic reinforcement structure includes one or more plastic sidewalls that protect the edges of the lid from damage. The upper and lower surfaces of t... | 07/06/2010 |
| 7737390 | Horizontal row drivers for CMOS image sensor with tiling on three edges A large image sensor structure is created by tiling a plurality of image sensor dies, wherein each of the image sensor dies includes a pixel array that extends to three edges of the die, and control circuitry located along a fourth edge of the die. None of the contr... | 06/15/2010 |
| 7721679 | Vapor generator with preheater and method of operating same An efficient high-temperature water vapor generator includes a combustion chamber and a surrounding structure, wherein a cavity is located therebetween. Water is pumped into the cavity at a location near a first end of the combustion chamber. Water is removed from t... | 05/25/2010 |
| 7684229 | Scalable embedded DRAM array A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor ... | 03/23/2010 |
| 7682907 | Non-volatile memory integrated circuit A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells str... | 03/23/2010 |
| 7671401 | Non-volatile memory in CMOS logic process A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capaci... | 03/02/2010 |
| 7671396 | Three-dimensional control-gate architecture for single poly EPROM memory devices fabricated in planar CMOS technology A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is... | 03/02/2010 |
| 7669360 | Fishing system An improved fishing system that records ambient conditions existing at or around the time a fish is caught. The fishing system includes a lure which records ambient conditions, including time, date, depth, temperature, ambient light, an underwater picture of a hooke... | 03/02/2010 |
| 7646028 | LED driver with integrated bias and dimming control storage A LED driver IC includes a control module(s) for controlling one or more LED drive parameters and non-volatile memory for storing settings data for that control module(s). The control module(s) is fully integrated into the LED driver IC and does not require any cont... | 01/12/2010 |
| 7634707 | Error detection/correction method A method for error detection and correction (EDC) includes: generating a complete EDC code in response to a data packet; distributing the complete EDC code among the data packet to create a plurality of bytes, each including a data portion from the data packet and a... | 12/15/2009 |
| 7633811 | Non-volatile memory embedded in a conventional logic process and methods for operating same A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the sourc... | 12/15/2009 |
| 7633810 | Non-volatile memory embedded in a conventional logic process and methods for operating same A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the sourc... | 12/15/2009 |
| 7633114 | Non-volatile memory integrated circuit A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells str... | 12/15/2009 |
| 7631201 | System software for managing power allocation to Ethernet ports in the absence of mutually exclusive detection and powering cycles in hardware A method of allocating power to ports in an Ethernet switch, including: (1) determining the available capacity of a power pool used to supply the ports, (2) assigning a configuration power to each of the ports, (3) selecting a port to be enabled, (4) determining whe... | 12/08/2009 |
| 7616501 | Method for reducing charge loss in analog floating gate cell A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly conn... | 11/10/2009 |
| 7609093 | Comparator with low supply current spike and input offset cancellation A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is bi... | 10/27/2009 |
| 7608837 | High resolution integrated X-ray CMOS image sensor An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a dist... | 10/27/2009 |
| 7602232 | Programmable fractional charge pump for DC-DC converter A charge pump provides a programmable multiplication factor for generating an output voltage. A first output voltage may be generated by connecting a first plurality of N capacitors in a first plurality of (N+1) configurations. A second output voltage may be generat... | 10/13/2009 |
| 7564283 | Automatic tap delay calibration for precise digital phase shift An automatic calibration scheme is provided, which calibrates the equivalent taps per period ETT/P every time a delay lock loop is used. More specifically, a digital phase shifter is used to measure equivalent taps per period ETT/P. Alternately, the digital phase sh... | 07/21/2009 |
| 7558111 | Non-volatile memory cell in standard CMOS process A non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-N... | 07/07/2009 |
| 7558108 | 3-bit NROM flash and method of operating same Operation of conventional nitride read-only-memory (NROM) cells is modified, such that each charge trapping region of an NROM cell is capable of storing any one of three charge states. For example, each charge trapping region can have an erased state, a first progra... | 07/07/2009 |
| 7557641 | Fractional charge pump for step-down DC-DC converter A charge pump provides a multiplication factor of ⅔ by using a three-phase mode of operation. In a first mode, first and second capacitors are charged from an input voltage while a third capacitor drives the output voltage based on stored charge in the third capac... | 07/07/2009 |
