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"Transmission of documents via telephone wires is possible in principle, but the apparatus required is so expensive that it will never become a practical proposition."
Dennis Gabor, British physicist
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| Number | Title | Issue Date |
| 8175100 | Transmission scheduling optimization method and wireless user equipment device A wireless user equipment device transmits a control channel and a data channel. Each of the control channel and the data channel include a plurality of time slots. The control channel is configured to transmit control information and includes both transmission time... | 05/08/2012 |
| 8171192 | Hardware-assisted device configuration detection A method and apparatus for detecting the configuration of a device in a processing system are described. In one embodiment, a page size parameter associated with a memory device is identified. Further, one or more configuration parameters associated with the memory ... | 05/01/2012 |
| 8170506 | Direct current (DC) offset correction using analog-to-digital conversion Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide ... | 05/01/2012 |
| 8169243 | Techniques for non-overlapping clock generation Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in tu... | 05/01/2012 |
| 8165619 | Power allocation for power control bits in a cellular network A power allocation value for power control information transmitted from a first station to a plurality of stations is determined by receiving data rate control information from the plurality of stations in a communications system. Supplemental information relating t... | 04/24/2012 |
| 8164369 | Techniques for minimizing control voltage noise due to charge pump leakage in phase locked loop circuits Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump output noise in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a ... | 04/24/2012 |
| 8164361 | Low power complementary logic latch and RF divider A quadrature output high-frequency RF divide-by-two circuit includes a pair of differential complementary logic latches. The latches are interconnected to form a toggle flip-flop. Each latch includes a tracking cell and a locking cell. In a first embodiment, the loc... | 04/24/2012 |
| 8160513 | Methods and apparatus for implementing phase rotation at baseband frequency for transmit diversity An apparatus for implementing phase rotation at baseband frequency for transmit diversity may include a primary transmit signal path and a diversity transmit signal path. Both the primary transmit signal path and the diversity transmit signal path may receive a prim... | 04/17/2012 |
| 8160031 | Method for power control for mixed voice and data transmission Power control of mixed voice and data transmissions is disclosed. A voice signal is transmitted at a dynamically-adjusted voice transmit power capped at a maximum voice transmit power limit. Concurrently, data bursts are transmitted on top of the voice signal. Data ... | 04/17/2012 |
| 8160015 | Systems and methods for measuring and reducing latency of radio link flows Disclosed are systems, methods and computer program products for measuring and reducing latency of radio link flows having different quality of service (QoS) reservations. An example method comprises establishing one or more radio link flows with an access gateway, ... | 04/17/2012 |
| 8149023 | RF buffer circuit with dynamic biasing An RF buffer circuit for a voltage controlled oscillator (VCO) includes dynamic biasing circuitry to selectively flip the phase of the output voltage waveform. In a CMOS implementation, a PMOS/NMOS pair is employed in an output path. During a high (voltage) swing mo... | 04/03/2012 |
| 8145171 | Clock clean-up phase-locked loop (PLL) A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a first clock signal generated... | 03/27/2012 |
| 8144042 | Combinatorial circuit with shorter delay when inputs arrive sequentially and delta sigma modulator using the combinatorial circuit A combinatorial circuit with pre-calculation and having shorter delay is described. The combinatorial circuit uses information available from earlier input signals to pre-calculate intermediate signals, which are used to generate output signals when the last input s... | 03/27/2012 |
| 8140026 | All-digital selectable duty cycle generation All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency... | 03/20/2012 |
| 8139518 | System for measuring a rise-over-thermal characteristic in a communication network A system for measuring a rise-over-thermal (RoT) characteristic in a communication network includes controlling a transmitting station to maintain its transmit power at a substantially constant level for a first time interval, and measuring a first received power le... | 03/20/2012 |
| 8135055 | I/Q calibration of transmit and receive paths in OFDM FDD communication systems I/Q gain and phase mismatches of both transmit and receive paths of an OFDM FDD transceiver are simultaneously estimated. An up-converted RF signal is generated when the transmit path performs IQ modulation on a reference signal having a single sideband tone. The up... | 03/13/2012 |
| 8132041 | Method and apparatus for generating or utilizing one or more cycle-swallowed clock signals An electronic device is provided for generating or utilizing one or more cycle-swallowed clock signals derived based on one or more first clock signals. The device includes a module configured to receive a first clock signal having a first frequency. The module is c... | 03/06/2012 |
| 8130046 | Frequency calibration of radio frequency oscillators A wireless communication device incorporating a set of comparators and logic interrupt into the local oscillator generation circuit block is described. In one design, the local oscillator circuit block includes a RF VCO with coarse and fine frequency tuning. The RF ... | 03/06/2012 |
| 8130020 | Switched-capacitor decimator A switched-capacitor decimator that can attenuate undesired signal components at odd harmonics of an output sample rate is described. In one design, the switched-capacitor decimator includes at least one sampling capacitor and multiple switches. For each sampling ca... | 03/06/2012 |
| 8106809 | Sigma-delta converters and methods for analog-to-digital conversion A switched capacitor sigma-delta modulator or another analog-to-digital converter (ADC) uses chopper stabilization. Chopping clock transitions are performed during non-active periods of the sampling clock phases, reducing disturbance of the circuit caused by choppin... | 01/31/2012 |
| 8099127 | Multi-mode configurable transmitter circuit Method and apparatus for configuring a transmitter circuit to support multiple modes and/or frequency bands. In an embodiment, a pre-driver amplifier (pDA) in a transmit (TX) signal path is selectively bypassed by a controllable switch. The switch can be controlled ... | 01/17/2012 |
| 8098779 | Interference detection and mitigation Techniques for detecting and mitigating interference are described. A device (e.g., a cellular phone) senses interference levels and digitally reconstructs the expected interference in the received signal. The device may correlate the reconstructed interference with... | 01/17/2012 |
| 8098718 | Apparatus and methods for digital-to-analog conversion with vector quantization A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sort... | 01/17/2012 |
| 8078122 | Interface between digital and analog circuits Circuitry that generates an interface signal between a first and a second integrated circuit (IC). The circuitry includes a reference circuit that provides a reference signal, an interface circuit, and a circuit element. The interface circuit is implemented on the f... | 12/13/2011 |
| 8044746 | Flexible interconnect cable with first and second signal traces disposed between first and second ground traces so as to provide different line width and line spacing configurations A high speed flexible interconnect cable for an electronic assembly includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high spee... | 10/25/2011 |
| 8044723 | Oscillator signal generation with spur mitigation in a wireless communication device Techniques for generating oscillator signals in a wireless communication device are described. A phase-locked loop (PLL) may be used to generate an oscillator signal for a selected frequency channel. Different PLL settings may be used for the blocks in the PLL for d... | 10/25/2011 |
| 8031019 | Integrated voltage-controlled oscillator circuits Techniques for providing voltage-controlled oscillator circuits having improved phase noise performance and lower power consumption. In an exemplary embodiment, a voltage controlled oscillator (VCO) is coupled to a mixer or a frequency divider such as a divide-by-tw... | 10/04/2011 |
| 8023280 | Communication circuit for driving a plurality of devices A system and method is provided for transmitting a signal to a plurality of slave devices (e.g., memory devices, etc.) via a communication circuit having a plurality of segments that are substantially equal in length and/or impedance. Specifically, according to one ... | 09/20/2011 |
| 8022772 | Cascode amplifier with protection circuitry A cascode amplifier with protection circuitry is described. In one exemplary design, the amplifier includes multiple branches coupled in parallel, with at least one branch being switchable between “on” and “off” states. Each switchable branch includes a gain... | 09/20/2011 |
| 8000326 | Method and apparatus for fragmenting a control message in wireless communication system Techniques for sending control information are described. In an aspect, information to send in a control message may be fragmented into multiple parts, with each part including information of a particular type. The multiple parts may be segregated into multiple cate... | 08/16/2011 |
| 7995671 | Multiple-input multiple-output (MIMO) transmission with rank-dependent precoding Techniques for performing rank-dependent precoding for a multiple-input multiple-output (MIMO) transmission are described. Each rank may be associated with a set of at least one precoding vector or matrix that can provide good performance for that rank. A transmitte... | 08/09/2011 |
| 7978111 | High resolution time-to-digital converter A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile o... | 07/12/2011 |
| 7973612 | Supply-regulated phase-locked loop (PLL) and method of using A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling capacitor array is adjustable ... | 07/05/2011 |
| 7965111 | Method and apparatus for divider unit synchronization A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a ... | 06/21/2011 |
| 7961724 | Dynamic media access control (MAC) address assignment According to the invention an embodiment, a network node for communicating using a MAC address is disclosed. The network node includes a point-to-point interface, a bridge and a MAC address register. The point-to-point interface uses a first protocol. The bridge is ... | 06/14/2011 |
| 7961592 | Method and apparatus for transmitting and receiving variable rate data A variable rate transmission system transmits a variable rate data packet including an accompanying rate indication signal indicative of the transmission rate of the variable data packet. The data packet can be spread using a long pseudonoise (PN) code, the mask of ... | 06/14/2011 |
| 7839882 | Resource allocation in a wireless communication system Method and apparatus for scheduling transmissions in a wireless communication system using historical information and usage patterns of remote users in the system. Usage patterns for users within a system are stored and analyzed to optimize transmissions and resourc... | 11/23/2010 |
| 7835695 | Method and apparatus for determining the closed loop power control set point in a wireless packet data communication system According to one aspect of the invention, a method for determining a power control set point is provided. In one embodiment, the power control set point is determined based on one or more factors including a first factor corresponding to a pilot bit error rate, a se... | 11/16/2010 |
| 7826418 | Block-based assignment of quality of service precedence values An ordered list of precedence values includes a number of blocks of precedence values. An operating system receives filters from an application. The operating system assigns a precedence value to each filter from the available block of precedence values that has the... | 11/02/2010 |
| 7796563 | Method and system for selecting a best serving sector in a CDMA data communication system An apparatus for selecting a best serving sector in a code division multiple access (CDMA) communication system. A comparator compares a plurality of signal levels received from a plurality of active sectors with a signal level of a current serving sector to produce... | 09/14/2010 |
