Decorative Jeweled Wheel Cover
An improved wheel is provided wherein decorative items such as gem stones are embedded in either the wheel surface, a special mounting section attached to the wheel surface, or to a spoke strap that wraps around each spoke and positions embedded gem stones on the outside surface of the spoke.
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| Number | Title | Issue Date |
| 6016384 | Method for speeding up the convergence of the back-propagation algorithm applied to realize the learning process in a neural network of the multilayer perceptron type A method for speeding up the convergence of the back-propagation algorithm applied to realize the learning process in a neural network of the multilayer perceptron type intended for instance to recognize a set of samples. The method comprises a first stag... | 01/18/2000 |
| 5655065 | Mask generator usable with addressing schemes in either big endian or little endian format A mask generator for use with at least first and second addressing schemes in a microprocessor system, wherein a first addressing scheme is in little endian format and a second addressing scheme is in big endian format. The mask generator, based upon data... | 08/05/1997 |
| 5644518 | Computing device for nth degree functions An nth degree function computing device having a low-cost, small scale circuit in which no multipliers are present and which allows high-speed computing operations. The nth degree function computing device comprises two series operators 32 and 38 connecte... | 07/01/1997 |
| 5642001 | Overdrive circuit An overdrive circuit having a first current source which supplies an overdrive current and a second current source which supplies an ordinary current smaller than the overdrive current. A first circuit operates the first current source that supplies the o... | 06/24/1997 |
| 5635776 | Charge pump voltage converter A charge pump circuit which has a simple circuit configuration yet can boost the power source voltage 4 or 8 times. The + side electrode of a capacitor C1 is connected to an input terminal 10 via a diode D1; the - side electrode is connected to input term... | 06/03/1997 |
| 5625234 | Semiconductor memory device with bit line and select line arrangement maintaining parasitic capacitance in equilibrium A semiconductor memory device in which sensing of the memory information stored in a memory cell can be carried out stably, and reliably by equilibrating a parasitic capacitance existing between a select line and its adjacent bit line pair. Each Y select ... | 04/29/1997 |
| 5623123 | Semiconductor device package with small die pad and method of making same Semiconductor device package 53 having a lead frame with a mounting pad 31 smaller than the IC chip 10 mounted thereon, and a method of making a semiconductor device package based on wire bonding using a heater insert 38 with a mounting pad insertion conc... | 04/22/1997 |
| 5615156 | Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approxi... | 03/25/1997 |
| 5610546 | Controlled delay circuit Delay circuit comprising a delay cell formed by a current source (I) connected between drain and source of two field-effect transistors (PO, NO) whose gates are connected to each other in order to constitute the input of the cell, and an inverter (INV) li... | 03/11/1997 |
| 5603049 | Bus system servicing plural module requestors with module access identification known to system user An integrated circuit having a plurality of modules and an internal communication bus interconnecting the modules is arranged to produce an output indicating which module is granted access to the bus at the time. A control means grants to a module access ... | 02/11/1997 |
| 5600176 | Integrated voltage divider Integrated voltage divider comprising partial resistors (R1 ,R2) formed of paths of polycrystalline semiconductor material applied over a dielectric layer (4) on a semiconductor substrate (5). Under the paths, each forming a partial resistor (R1,R2) in th... | 02/04/1997 |
| 5596537 | Semiconductor device test circuit having test enable circuitry and test mode-entry circuitry A semiconductor device test circuit for inclusion on a semiconductor chip having a semiconductor device thereon, wherein a test mode with respect to the semiconductor device is not entered during normal use of the semiconductor device and the test mode ca... | 01/21/1997 |
| 5594279 | Semiconductor device having shield wiring for noise suppression A semiconductor device in which shield wiring is arranged between the semiconductor substrate and the power source wiring for supplying the power source potential or ground potential. Noise, as represented by variations in the potential of the semiconduct... | 01/14/1997 |
| 5572114 | Current mirror circuit with bipolar transistor connected in reverse arrangement A semiconductor integrated circuit for performing a current mirror function and capable of operating stably at a low supply voltage to yield an output current nearly equal to the reference current. The current mirror circuit includes a pair of horizontal ... | 11/05/1996 |
| 5570008 | Band gap reference voltage source For compensating the Early effect a band gap reference voltage source includes current mirror circuits (T4, Q3 and T1, Q1 as well as T2, Q2) to ensure that the currents necessary for achiev... | 10/29/1996 |
| 5563433 | French-type semiconductor memory device with enhanced trench capacitor-transistor connection A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film (54), and an electroconductive layer (63) with step from the aforemention... | 10/08/1996 |
| 5563959 | Character recognition This invention relates to a method and apparatus for recognizing a script written character. The character is entered using character entering means and digitised by appropriate means. The digitised character is then stored in, for example, a memory. Code... | 10/08/1996 |
| 5557580 | Word line driving circuit A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit include... | 09/17/1996 |
| 5554443 | Bonding wire with heat and abrasion resistant coating layers A resin-coated, bonding fine wire for use in forming bonded electrical connections on a semiconductor device, wherein the bonding wire comprises an elongated fine wire of electrically conductive material, and first and second non-conductive coating layers... | 09/10/1996 |
| 5550401 | Lead on chip semiconductor device having bus bars and crossing leads Along the column of bonding pad (1), bonding terminal portions (2c), (3c), (4a), (5a) of bus bars (2), (3), and signal lines (4), (5) are arranged; principal wiring portions (2a), (3a) are made to extend in a 3-dimensional crossing configuration with resp... | 08/27/1996 |
| 5550394 | Semiconductor memory device and defective memory cell correction circuit To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant ... | 08/27/1996 |
| 5546053 | Phase locked loop having booster circuit for rapid lockup A frequency adjusting circuit having a voltage-controlled oscillator in which the lockup time is shortened. The voltage waveform appearing at the two terminals of a resistor element R1 of a low-pass filter 6 is subject to voltage/current conver... | 08/13/1996 |
| 5544104 | Virtual crosspoint memory An interconnection-point memory which includes an array of N1 input buses (Rj) intended to be connected to a first plurality of N1 data-sender devices, an array of N2 output buses (Ck) intended to be connected to a second plurality of N2 data-receiver dev... | 08/06/1996 |
| 5543612 | Image pickup device with attached interference stripe noise prevention mechanism An image pickup device providing favorable images which effectively suppress the interference stripe noise originating in the interference stripes created on an image sensor surface of the image pickup device. The image pickup device includes an image sen... | 08/06/1996 |
| 5541938 | Method and apparatus for mapping memory as to operable and faulty locations System for enabling the use of semiconductor dynamic memories having faulty locations therein where the memory is organized in banks for forming an elementary information word. The system identifies all homologous address locations which are not faulty, a... | 07/30/1996 |
| 5532946 | Calculator with table generation capability A digital computer or calculator (10) is equipped with a numerical data table generation capability (36). It provides a user with the ability to specify one or more mathematical functions (32), and the ability to specify how the numerical data in support ... | 07/02/1996 |
| 5525958 | Electronic appointment organizer with paper pad for providing handwritten information correlated to appointments An appointment reminder (10) includes a display (12) for displaying one or more appointment identifiers (14), the time of day, and the day of week. A keyboard (17) has an appointment key for initiating an appointment setting program and set keys (16) for ... | 06/11/1996 |
| 5523962 | Infinite impulse response digital filter with plural processing units A digital filter, in which the operation time can be kept short even when the order of the filter is high. The digital filter comprises a first transversal filter TF1 which has an input terminal connected to a signal input terminal 10, first de... | 06/04/1996 |
| 5523568 | Image signal processing method in scanning electron microscope and device thereof An image signal processing method in which inspection of a specimen is performed based on the image data collected for the wafer or other specimen by scanning a pilot specimen in a scanning electron microscope, prior to the scanning of the specimen to be ... | 06/04/1996 |
| 5521953 | Shift register with transfer gate-inverter arrangement providing stable operation A shift register which is stably operable even under low power voltage and including a first transfer gate NTM1 connected to a data input terminal DIN1, second and third transfer gates NTM2 and NTM3 connected in series to a ground line, a pair of inverter... | 05/28/1996 |
| 5519456 | Motion detecting circuit and noise reducing circuit utilizing polarity determination for pixel block of a video display A motion detecting circuit and a noise reducing circuit of high reliability and independent of the magnitude of motion, presence/absence of noise, and magnitude of the noise. The motion detecting circuit includes a subtractor 14 which receives as inputs, ... | 05/21/1996 |
| 5517451 | Semiconductor memory device and memory initializing method A semiconductor memory device and an initialization method therefor, wherein writing of the initialization data into memory cells of the semiconductor memory device can be performed in a simple way in a short period of time. When initialization is perform... | 05/14/1996 |
| 5514898 | Semiconductor device with a piezoresistive pressure sensor A semiconductor device comprises a piezoresistive pressure sensor (12), which has a membrane (14), which is constituted by a conducting epitaxy layer (16), which is applied to a conducting semiconductor substrate (18) of the opposite conductivity. On the ... | 05/07/1996 |
| 5504911 | Bus system servicing plural module requestors with module access identification An integrated circuit having a plurality of modules and an internal communication bus interconnecting the modules is arranged to produce an output indicating which module is granted access to the bus at the time. A control means grants to a module access ... | 04/02/1996 |
| 5502808 | Video graphics display system with adapter for display management based upon plural memory sources Video graphics display system having a display adapter connected between a host processor (2) and a display unit (6). The display adapter includes a video memory (4) which has first and second memory parts (3) and (8). A graphics processor (1) is connecte... | 03/26/1996 |
| 5499028 | Analog/digital converter An analog/digital converter providing a high conversion speed and resolution while greatly reducing the number of circuit elements. The A/D converter in a first embodiment is a 6-bit resolution flash A/D converter made up of a 3-bit lower A/D conversion s... | 03/12/1996 |
| 5488288 | Circuit arrangement integrated in a semiconductor circuit The present invention relates to a circuit arrangement integrated in a semiconductor circuit. In modern microprocessor systems with high clock rates (50 MHz and more) special chips with narrow tolerance ranges as regards their switching speed are required... | 01/30/1996 |
| 5487040 | Semiconductor memory device and defective memory cell repair circuit To provide a type of semiconductor memory device characterized by the fact that the area occupied by the redundant memory address decoder on the chip is minimized without reducing the redundancy of the defective memory, and hence the cost of the semicondu... | 01/23/1996 |
| 5487039 | Semiconductor memory device A semiconductor memory device with a redundant circuit architecture having improved repairing efficiency and improved yield comprising a memory array (1) divided between a number of subarrays, in which a number of memory cells MCL are arrayed in matrix fo... | 01/23/1996 |
| 5483554 | Modulator especially for digital cellular telephone system Modulator especially for digital cellular telephone systems, characterised in that it comprises a programmable peripheral processor (25) carrying out, with the same circuits, the modulation function and the channel coder/decoder tasks.... | 01/09/1996 |