Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 7924131 | Electrical component having an inductor and a method of formation An electrical component (100) having an inductor includes: (a) a first substrate (102) comprising at least one first electrically conductive layer (108, 110, 112); (b) one or more second substrates (104, 106) comprising at least one secon... | 04/12/2011 |
| 7919006 | Method of anti-stiction dimple formation under MEMS A method for making a MEMS structure comprises patterning recesses in a dielectric layer overlying a substrate, each recess being disposed between adjacent mesas of dielectric material. A conformal layer of semiconductor material is formed overlying the recesses and... | 04/05/2011 |
| 7903483 | Integrated circuit having memory with configurable read/write operations and method therefor An integrated circuit having a memory and a method for operating the memory are provided. The method for operating the memory comprises: accessing a first portion of the memory, the first portion having a first access margin; detecting an error in the first portion ... | 03/08/2011 |
| 7872311 | Method and apparatus for mobility enhancement in a semiconductor device A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are... | 01/18/2011 |
| 7869609 | Bounded signal mixer and method of operation A method and apparatus are provided for mixing a plurality of signals within a predetermined dynamic range without clipping. In the method and apparatus, first and second signal samples are added together to obtain a first intermediate result. Then the first signal ... | 01/11/2011 |
| 7867858 | Hybrid transistor based power gating switch circuit and method A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having th... | 01/11/2011 |
| 7864617 | Memory with reduced power supply voltage for a write operation A memory includes a selection circuit and a write assist circuit. The selection circuit has a first input, a second input coupled to a first power supply voltage terminal, an output coupled to a power supply terminal of each of a plurality of memory cells, and a con... | 01/04/2011 |
| 7863963 | Level shifter for change of both high and low voltage A circuit comprises first and second inverters, first, second, third, and fourth transistors, and an enabling circuit. The first and second inverters each have an input terminal for receiving one of the first or second input signals, an output terminal, and first an... | 01/04/2011 |
| 7842573 | Virtual ground memory array and method therefor A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the ... | 11/30/2010 |
| 7833852 | Source/drain stressors formed using in-situ epitaxial growth A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent ... | 11/16/2010 |
| 7821055 | Stressed semiconductor device and method for making A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion ... | 10/26/2010 |
| 7805590 | Coprocessor receiving target address to process a function and to send data transfer instructions to main processor for execution to preserve cache coherence A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and... | 09/28/2010 |
| 7800959 | Memory having self-timed bit line boost circuit and method therefor A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair ... | 09/21/2010 |
| 7799678 | Method for forming a through silicon via layout A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stresse... | 09/21/2010 |
| 7799634 | Method of forming nanocrystals Nanocrystals are formed over an insulating layer by depositing a semiconductor layer over the insulating layer. The semiconductor layer is annealed to form a plurality of globules from the semiconductor layer. The globules are annealed using oxygen. Semiconductor ma... | 09/21/2010 |
| 7796688 | Radio receiver having a channel equalizer and method therefor A radio receiver for receiving a signal is provided. The radio receiver comprises an equalizer configured to perform a constant modulus algorithm initialized using a first set of coefficients on the received signal and for generating an equalized signal. The radio r... | 09/14/2010 |
| 7795951 | High-dynamic range low ripple voltage multiplier A voltage multiplier (10) including a first clocked multiplier stage (12) having an input and an output and a second clocked multiplier stage (14, 16) having an input and an output is provided. The voltage multiplier further includes an input le... | 09/14/2010 |
| 7795904 | Switching circuit having a driver for providing a linear voltage transition A switching circuit includes a first transistor and a driver circuit. The first transistor has a first current electrode coupled to a first power supply voltage terminal to receive a first power supply voltage, a control electrode, and a second current electrode cou... | 09/14/2010 |
| 7791389 | State retaining power gated latch and method therefor A circuit has first latch, a second latch, a coupling circuit, and a power down circuit. The first latch has an input/output coupled to a data node. The second latch has an input/output. The coupling circuit is coupled between the input/output of the second latch an... | 09/07/2010 |
| 7787323 | Level detect circuit A detect circuit may be used to detect one or more characteristics corresponding to the fuse being programmed. When the one or more characteristics of the fuse being programmed reach the desired states or values, the programming of the fuse is discontinued. Thus, th... | 08/31/2010 |
| 7785983 | Semiconductor device having tiles for dual-trench integration and method therefor A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are differen... | 08/31/2010 |
| 7782664 | Method for electrically trimming an NVM reference cell An integrated circuit memory has a plurality of non-volatile memory cells and a reference cell. The reference cell provides a reference current for reading a selected memory cell of the plurality of non-volatile memory cells. A method comprises trimming the referenc... | 08/24/2010 |
| 7781831 | Semiconductor device having nitridated oxide layer and method therefor A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15 | 08/24/2010 |
| 7777522 | Clocked single power supply level shifter First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes ref... | 08/17/2010 |
| 7737740 | Integrated circuit with a programmable delay and a method thereof An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block havin... | 06/15/2010 |
| 7736957 | Method of making a semiconductor device with embedded stressor A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode... | 06/15/2010 |
| 7705555 | Method and controller for detecting a stall condition in a stepping motor during micro-stepping A method is provided for detecting a stall condition in a stepping motor. The stepping motor has two coils and a rotor, and is micro-stepped by substantially continuously driving both of the two coils with out-of-phase time varying voltages. The method includes step... | 04/27/2010 |
| 7698353 | Floating point normalization and denormalization A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is par... | 04/13/2010 |
| 7692989 | Non-volatile memory having a static verify-read output data path A memory has first and second memory arrays and first and second sense amplifiers coupled to the first and second memory arrays, respectively. A verify data line is coupled to first outputs of the first sense amplifier and the second sense amplifier as well as to a ... | 04/06/2010 |
| 7688656 | Integrated circuit memory having dynamically adjustable read margin and method therefor A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, including a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin correspondin... | 03/30/2010 |
| 7676204 | Radio receiver having ignition noise detector and method therefor An AM receiver including an AM demodulator for demodulating an AM signal received by an antenna coupled to the AM demodulator is provided. The AM receiver further includes a bandpass filter for receiving the demodulated signal and generating a bandpass filtered sign... | 03/09/2010 |
| 7671629 | Single-supply, single-ended level conversion circuit for an integrated circuit having multiple power supply domains A circuit comprises first, second, third, and fourth transistors. The first transistor has a first current electrode, a control electrode for receiving an input signal, and a second current electrode. The second transistor has a first current electrode coupled to th... | 03/02/2010 |
| 7668029 | Memory having sense time of variable duration In one form a memory and method thereof has a memory array having a plurality of memory cells. A bit line precharge operation is based on a clock edge of an external clock signal. A word line is selected after the beginning of the precharge operation. A sense operat... | 02/23/2010 |
| 7655550 | Method of making metal gate transistors A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal pro... | 02/02/2010 |
| 7640389 | Non-volatile memory having a multiple block erase mode and method therefor A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to differe... | 12/29/2009 |
| 7639097 | Crystal oscillator circuit having fast start-up and method therefor In one embodiment, a method of programming an oscillator circuit includes providing a resonator, a first programmable capacitor, a second programmable capacitor, and an amplifier. The first programmable capacitor and the second programmable capacitor may be programm... | 12/29/2009 |
| 7630272 | Multiple port memory with prioritized world line driver and method thereof A multiple port memory has a word line driver that provides a word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation. A first logic circuit has a first input for receiving a fir... | 12/08/2009 |
| 7629840 | Digital pulse width modulated feedback system for a switching amplifier and method therefor A switching amplifier includes a power stage, a low pass filter, a combining circuit, and a feedback correction circuit. The power stage has an input terminal and an output terminal. The low pass filter has an input terminal coupled to the output terminal of the pow... | 12/08/2009 |
| 7619440 | Circuit having logic state retention during power-down and method therefor A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled... | 11/17/2009 |
| 7586238 | Control and testing of a micro electromechanical switch having a piezo element A micro electromechanical switch has a movable portion positioned to form an electrical connection between a first electrical contact and a second electrical contact. A piezoelectric electrode is formed on the movable portion. The piezoelectric electrode causes the ... | 09/08/2009 |
