Bizarre Patents
User-operated amusement apparatus for kicking the user's buttocks
An apparatus including a user-operated and controlled apparatus for self-infliction of repetitive blows to the user's buttocks by a plurality of elongated arms bearing flexible extensions that rotate under the user's control.
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| Number | Title | Issue Date |
| 8179159 | Configuration interface to stacked FPGA A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a fra... | 05/15/2012 |
| 8146028 | Duplicate design flow for mitigation of soft errors in IC operation An integrated circuit (“IC”) (100) is configured to have two instantiations of a user design (103, 105). Register values from the first instantiation (RA1, RA2, RA3, RA4) are compared (102) to corresponding regist... | 03/27/2012 |
| 8143532 | Barrier layer to prevent conductive anodic filaments A through hole is formed in a circuit board that has fibers dispersed in a polymer matrix. Copper is sputtered within the through hole to form a sufficiently conductive layer for electrolytic plating over the sputtered copper layer. ... | 03/27/2012 |
| 8134813 | Method and apparatus to reduce footprint of ESD protection within an integrated circuit An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to... | 03/13/2012 |
| 8122177 | Direct memory access technique for use with PCIe endpoints An integrated circuit (“IC”) includes a peripheral component interconnect express (“PCIe”) root complex having a central processing unit (“CPU”), a memory controller configured to control a main memory of a PCIe system, and a PCIe port coupled to a PCIe ... | 02/21/2012 |
| 8121826 | Graphical user interface for system design A design tool for designing a system includes a display device with a first visualization pane showing a symbolic representation of a connection between a first port and a second port of the system and a second visualization pane showing an unconnected port of the s... | 02/21/2012 |
| 8121240 | Statistical measurement of average edge-jitter placement on a clock signal Phase shift is added between a uttering clock signal and a data bit stream clocked by the clock signal. The phase shift is adjusted until half the data bits are captured (counted) over a measurement period. Adding this amount of phase shift between the clock and dat... | 02/21/2012 |
| 8120430 | Stable VCO operation in absence of clock signal A semiconductor device having a phase-locked loop (“PLL”) (100) drives a VCO (114) of the PLL circuit with a first control voltage (VCTRL) produced by a loop filter (112) when a first clock signal (clk_ref) is present. The VCO pro... | 02/21/2012 |
| 8082535 | Method and apparatus for testing programmable integrated circuits A method of testing an IC generates a test design list of test patterns and produces an arc usage string for each test pattern. The arc usage strings are ranked according to the number of untested arcs in each successive test pattern by comparing each of the remaini... | 12/20/2011 |
| 8030954 | Internal voltage level shifting for screening cold or hot temperature defects using room temperature testing Operation of an internal voltage supply level (Vgg) of an IC is characterized over operating temperature or at a selected temperature to determine a temperature-equivalent internal voltage level. The internal voltage supply of the IC is set to the temperature-equiva... | 10/04/2011 |
| 8019019 | DC balance compensation for AC-coupled circuits A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is c... | 09/13/2011 |
| 8014184 | Radiation hardened memory cell A memory cell has a data value storage circuit and a data address circuit that includes a first address transistor formed in a first address transistor well and a second address transistor formed in a second address transistor well. The first address transistor is c... | 09/06/2011 |
| 8000519 | Method of metal pattern inspection verification A method of evaluating an inline inspection recipe compares the capture rate of metal pattern defects in bounding boxes arising from failed electrical test vectors to the capture rate after the bounding box is shifted. A difference between the first and second captu... | 08/16/2011 |
| 7994610 | Integrated capacitor with tartan cross section A capacitor in an IC has a first layer of conductive strips extending along a first direction (Z-direction). A first plurality of conductive strips in the first layer forms a portion a first node of the capacitor and alternates with a second plurality of conductive ... | 08/09/2011 |
| 7994609 | Shielding for integrated capacitors A capacitor in an integrated circuit (“IC”) includes a core capacitor portion having first conductive elements electrically connected to and forming a part of a first node of the capacitor formed in a first layer and second conductive elements electrically conne... | 08/09/2011 |
| 7984412 | IC design estimation using mid-level elements of IP cores A method (100) of estimating a performance characteristic of an integrated circuit (IC) design having an intellectual property (“IP”) core pre-characterizes an element type of the IC design to provide an estimation result of the element type (102- | 07/19/2011 |
| 7973555 | Configuration interface to stacked FPGA A semiconductor device includes a field-programmable gate array (“FPGA”) die (202) having a frame address bus (604), a frame data bus (608), and a second integrated circuit (“IC”) die (204) attached to the FPGA die. An inter-chip ... | 07/05/2011 |
| 7956438 | Integrated capacitor with interlinked lateral fins A capacitor in an integrated circuit (“IC”) has a first node conductor formed in a first metal layer of the IC with a first spine extending along a first direction, a first vertical element extending from the first spine along a second direction perpendicular to... | 06/07/2011 |
| 7949790 | Machines for inserting or removing fixed length data at a fixed location in a serial data stream A method of modifying a data stream (12) in an integrated circuit (“IC”) determines a modification point (14) in the data stream from a beginning (16) of the data stream. The modification point is within a word (W7) and has an offset ... | 05/24/2011 |
| 7947980 | Non-volatile memory cell with charge storage element and method of programming An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate... | 05/24/2011 |
| 7944732 | Integrated capacitor with alternating layered segments A capacitor in an integrated circuit (“IC”) has a first node plate link formed in a first metal layer of the IC electrically connected to and forming a portion of a first node of the capacitor extending along a first axis (y) and a second node plate link formed ... | 05/17/2011 |
| 7936006 | Semiconductor device with backfilled isolation An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric structure underlies the channel region of a MOS device, as well as th... | 05/03/2011 |
| 7932563 | Techniques for improving transistor-to-transistor stress uniformity An integrated circuit has a transistor with an active gate structure overlying an active diffusion area formed in a semiconductor substrate. A dummy gate structure is formed over a diffusion area and separated from the active gate structure by a selected distance (d... | 04/26/2011 |
| 7930661 | Software model for a hybrid stacked field programmable gate array A software model (620) of a stacked integrated circuit system (600) includes a first integrated circuit die (602) connected to a second integrated circuit die (604) through an interchip communication interface (606). A software mod... | 04/19/2011 |
| 7923811 | Electronic fuse cell with enhanced thermal gradient An electronic fuse (“E-fuse”) cell is formed on a semiconductor substrate. The E-fuse cell has a fuse element with a fuse link extending from a first fuse terminal across a thick dielectric structure to a second fuse terminal. The first and second fuse terminals... | 04/12/2011 |
| 7902477 | Integrated circuit test work station A test work station for testing ICs includes an output bench with sliding rails that partitions the table top of the output bench into segregated areas. ICs that pass testing are sorted according to an operating parameter, in other words binned, and placed in the ap... | 03/08/2011 |
| 7893712 | Integrated circuit with a selectable interconnect circuit for low power or high performance operation An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage... | 02/22/2011 |
| 7888771 | E-fuse with scalable filament link An electronic fuse (“E-fuse”) has a silicide filament link extending along a gap between polysilicon structures formed on a silicon substrate. The silicide filament link extends across diffusions formed in the gap. A P-N junction between terminals of the E-fuse ... | 02/15/2011 |
| 7880265 | Packaged integrated circuit A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated ... | 02/01/2011 |
| 7875543 | Strain-silicon CMOS using etch-stop layer and method of manufacture Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide ... | 01/25/2011 |
| 7852757 | Status based data flow control for chip systems An integrated circuit (“IC”) with a peripheral component interconnect express (“PCIe”) has at least two data sinks (204, 206) and a data source (202) capable of providing data packets to either data sink. A switch (208) of the PCIe syste... | 12/14/2010 |
| 7852117 | Hierarchical interface for IC system An integrated circuit includes an auto-bridging architecture including a first phases block that interfaces to a first user block having a first user signal domain. The first phases block converts the first user signal domain to a common signal domain. A second phas... | 12/14/2010 |
| 7840919 | Resource mapping of functional areas on an integrated circuit The availability of device resources of an IC are quantified for a circuit design by building a representation of resource sites for the IC. Initial availability values are assigned to the resource sites, and any components having locking constraints are identified ... | 11/23/2010 |
| 7839693 | Method of fabricating CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. T... | 11/23/2010 |
| 7834659 | Multi-step programming of E fuse cells E-fuses in an E-fuse memory array are programmed by applying a first programming pulse to a plurality of E-fuses to program the plurality of E-fuses to a first state; and then applying a second programming pulse to at least a selected E-fuse in the plurality of E-fu... | 11/16/2010 |
| 7812642 | Pass gate with improved latchup immunity An integrated circuit includes a pass gate having an input and an output. An NMOS pass transistor is connected between the input and the output. The drain of the NMOS pass transistor is connected to the input and the source of the NMOS pass transistor is connected t... | 10/12/2010 |
| 7795900 | Memory array with multiple-event-upset hardening An integrated circuit has a memory array with a four-plex of SEU-hardened memory cells. Each of the SEU-hardened memory cells has an orientation different from each of the other SEU-hardened memory cells in the four-plex, and each of the SEU-hardened memory cells ha... | 09/14/2010 |
| 7790510 | Metal lid with improved adhesion to package substrate A metal lid for packaging semiconductor chips is stamped to form a sloped sidewall with a set-back from the edge of a package substrate. After the metal lid is placed over the semiconductor chip, molding compound is formed around portions of the exposed perimeter of... | 09/07/2010 |
| 7784004 | Skew lots for IC oscillators and other analog circuits Integrated circuits, key components in thousands of products, frequently include thousands and even millions of microscopic transistors and other electrical components. Because of difficulties and costs of fabricating these circuits, circuit designers sometimes ask ... | 08/24/2010 |
| 7755381 | Reducing noise on a supply voltage in an integrated circuit An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down (“de-tune”) data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some... | 07/13/2010 |
