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| Number | Title | Issue Date |
| 4866008 | Methods for forming self-aligned conductive pillars on interconnects Methods, of forming a self-aligned conductive pillar (16) on an interconnect (12) on a body (10) having semiconducting surfaces. A first mask (24) defines an inverse pattern for formation of an interconnect (12). The interconnect (12) is formed by additiv... | 09/12/1989 |
| 4866678 | Dual-port memory having pipelined serial output A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a grou... | 09/12/1989 |
| 4863878 | Method of making silicon on insalator material using oxygen implantation The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions wh... | 09/05/1989 |
| 4863559 | Method for forming local interconnects using chlorine bearing agents A method for etching titanium nitride local interconnects is disclosed. A layer of titanium nitride is formed as a by-product of the formation of titanium silicide by direct reaction; this layer of titanium nitride is present over the titanium silicide la... | 09/05/1989 |
| 4862421 | Sensing and decoding scheme for a BiCMOS read/write memory A BiCMOS static random access memory (SRAM) is disclosed, which has first and second stage sense amplifiers. Each column in the memory array is associated with a first stage sense amplifier, and the first stage sense amplifiers are arranged in groups, wit... | 08/29/1989 |
| 4862121 | Switched capacitor filter A biquadrature switched capacitor filter having differential input/output integrator amplifiers (12,34) and switched capacitor networks (16,28,36,40). The differential outputs of one amplifier (12) are crossed and connected to the switched capacitor netwo... | 08/29/1989 |
| 4862018 | Noise reduction for output drivers High current capacity output drivers for digital devices have output noise reduced and more quickly achieve stability by the insertion of resistance in series with inherent, parasitic inductance. The resistance may be one or more fixed resistances formed ... | 08/29/1989 |
| 4861421 | Photochemical semiconductor etching Laser (12) assisted photochemical etching of Hg1-x Cdx Te-type compounds (30) in solutions of bromine and other oxidants.... | 08/29/1989 |
| 4859626 | Method of forming thin epitaxial layers using multistep growth for autodoping control A method of forming thin epitaxial layers by subjecting a substrate to a high temperature prebake followed by a medium temperature capping seal and a low temperature deposition is disclosed. In a preferred embodiment the epitaxial layer is formed by low p... | 08/22/1989 |
| 4859012 | Optical interconnection networks Multichannel interconnection networks with optical deformable mirror devices as the reconfigurable switching element.... | 08/22/1989 |
| 4858183 | ECL high speed semiconductor memory and method of accessing stored information therein A hybrid ECL memory includes a hybrid memory array 36 which utilizes cross coupled CMOS latches (70). Each CMOS latch (70) is accessed by an ECL decoder (40) and an ECL Word Line driver (42) to read data therefrom. Data is accessed through a bipolar trans... | 08/15/1989 |
| 4858181 | Fast recovery PNP loaded bipolar static RAM memory cell with an independent current path A semiconductor memory includes a memory cell (42) which utilizes a cross-coupled bipolar SCR latch. The latch includes two sense nodes (78) and (80). Sense node (78) has associated therewith an NPN transistor (82) and a PNP load transistor (84). Similarl... | 08/15/1989 |
| 4858178 | Programmable sequence generator A programmable sequence generator comprises a combinatorial logic matrix (10,12) and an on-chip timer (24) having count lines (26) coupled as inputs to the logic matrix (10). Combinatorial logic functions may be programmed into the matrix having as variab... | 08/15/1989 |
| 4857835 | Global event qualification system Test logic may be included in the design of an integrated circuit (IC) to facilitate testability. In most instances, an IC's test logic can only be activated while the IC, or logic sections within the IC, are placed in a non-functional test mode. The pres... | 08/15/1989 |
| 4855244 | Method of making vertical PNP transistor in merged bipolar/CMOS technology A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried l... | 08/08/1989 |
| 4855685 | Precision switchable gain circuit A switchable gain circuit includes an operational amplifier (10) which has an input leg comprised of a series resistor (20) and an MOS transistor (22). A plurality of feedback legs are formed, each comprising one or more resistors that are equal in value ... | 08/08/1989 |
| 4855743 | Analog interface system An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital dat... | 08/08/1989 |
| 4855800 | EPROM with increased floating gate/control gate coupling Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between t... | 08/08/1989 |
| 4855617 | Schottky transistor logic floating latch flip-flop The disclosure relates to an STL flip flop circuit composed of a pair of latch circuits, the first latch circuit receiving R and S inputs and the clock signal and floating relative to the other latch circuit. The second latch circuit is referenced to grou... | 08/08/1989 |
| 4852059 | Content addressable memory A content addressable memory consists of a plurality of memory units each of which may be an integrated circuit. Each unit receives an input group of digits forming all or part of an input key code, and compares it simultaneously with a plurality of equal... | 07/25/1989 |
| 4852083 | Digital crossbar switch A digital crossbar switch for switching data from an input/output data bus to an internal data bus and to the same or another input/output data bus which includes a plurality of multiplexer logic units, an m-bit internal data bus coupled to each of said m... | 07/25/1989 |
| 4849757 | Integrated dual-slope analog to digital converter with r/c variance compensation A dual-slope A/D converter circuit has an oscillator (14) whose timing frequency is determined by the value of an oscillator resistor (70) and a oscillator capacitor (72). An integrator (66) integrates an input voltage at a rate determined by an integrati... | 07/18/1989 |
| 4845047 | Threshold adjustment method for an IGFET Polysilicon gate insulated gate field effect transistors with threshold adjustment implants made after the gate oxide (156) and a split of the polysilicon gate (158) have been formed provides a shallow, tight dopant profile.... | 07/04/1989 |
| 4842991 | Self-aligned nonnested sloped via A via (64, 66, 68) comprises a conductor (45, 46, 48) having a first surface (58, 60, 62) and at least one second surface (49) that forms at least one edge (52) with the first surface (58, 60, 62). A first insulator layer (33) is formed on the first surfa... | 06/27/1989 |
| 4843453 | Metal contacts and interconnections for VLSI devices Metal contacts and interconnections for integrated circuits utilize copper as the primary conductor, with the copper being totally encased in refractory metal layers on both top and bottom surfaces and also sidewalls. The contact hole in silicon oxide may... | 06/27/1989 |
| 4842675 | Integrated circuit isolation process A multiple recess isolation technology avoids stress induced defects while providing a substantially planar surface. A silicon substrate (10) is patterned and etched, creating active moat regions (18) and recesses (20a-b and 21a-b). The recesses are fille... | 06/27/1989 |
| 4839705 | X-cell EEPROM array An X-cell EEPROM array includes a plurality of common source regions (50) that each border on four gate regions (46), both formed at a face of a semiconductor substrate (10). Each gate region (46) further adjoins a common drain region (52). Each drain reg... | 06/13/1989 |
| 4839538 | Impact bipolar integrated circuit designed to eliminate output glitches caused by negative chip ground spikes The disclosure relates to a circuit for compensation for ground glitches in an integrated circuit wherein there is provided a glitch fix circuit wherein a node is responsive to a negative shift in the level of ground relative to Vcc to turn on a transisto... | 06/13/1989 |
| 4839633 | Asymmetric voltage monitor for series supplies Disclosed is a supply voltage monitor for detecting the asymmetric decay of one voltage source (Vdd) with respect to another voltage source (Vss). The monitor circuit (24) includes a resistive voltage divider (26) having a plurality ... | 06/13/1989 |
| 4839866 | Cascadable first-in, first-out memory A cascadable first-in, first-out memory unit (11, 12, 13) has a load/unload control (152) for write-addressing and read-addressing selected memory locations within its memory array (82). A write pointer (110, 112, 120) keeps track of the number of write o... | 06/13/1989 |
| 4839305 | Method of making single polysilicon self-aligned transistor A self-aligned, single polysilicon transistor is fabricated using nitride spacers (26, 68) to self-align the extrinsic base regions ( 48,80). The space between the base contacts (36,76) and the emitter contacts (34,78) is defined by the width of the nitri... | 06/13/1989 |
| 4837743 | Architecture for memory multiplexing A solid state memory system is arranged in a plurality of blocks of memory cells, the memory cells in each block arranged in columns and rows. When the memory system is addressed for a memory reference, block selection circuitry selects one block of the p... | 06/06/1989 |
| 4835528 | Cursor control system A cursor control system for computer displays moves a cursor unambiguously in three dimensions using a two dimensional input device. The plane of movement of the two dimensional device is divided into logical regions which correspond to movement along a t... | 05/30/1989 |
| 4835580 | Schottky barrier diode and method The preferred embodiments include Schottky barrier diode (80) clmaped bipolar transistors for use in planar integrated circuits with the diode (80) being formed in a trench to increase junction area, reduce series resistance from junction to the buried la... | 05/30/1989 |
| 4835738 | Register stack for a bit slice processor microsequencer A microsequencer includes a memory array (110) which is interfaced with a push/pop register (100). Data is input to the push/pop register (100) through a multiplexer (104) and also to Read register (102). The stack comprised of the RAM (110) and the regis... | 05/30/1989 |
| 4835115 | Method for forming oxide-capped trench isolation A method of forming trench isolation is disclosed. A trench is etched, either through field oxide or not, into the substrate, using an oxide hard mask. Implant of a channel-stop is then performed through a dummy sidewall oxide, followed by stripping of th... | 05/30/1989 |
| 4833514 | Planar FAMOS transistor with sealed floating gate and DCS+N2 O oxide The invention provides an EPROM having a high quality dielectric to separate the floating gate from low quality dielectric layers used in the prior art by the method outlined as follows. First, the polycrystalline silicon floating gates are formed and par... | 05/23/1989 |
| 4833399 | DTMF receiver A DTMF receiver (10) recognizes each of a plurality of multi-frequency tones, each tone centered on a predetermined standard frequency. Two digital bandpass filters (14, 16) each have four frequency bins, each frequency bin operating according to a recurs... | 05/23/1989 |
| 4831625 | Easily cascadable and testable cache memory The disclosure relates to a cache memory formed on a single chip wherein the ability to test the address comparator, cache memory diagnostics are improved, cache memory are capable of being read out. The architecture comprises a parity generator, a parity... | 05/16/1989 |
| 4831427 | Ferromagnetic gate memory A memory cell (10) comprises a ferromagnetic gate (12) disposed above a source (18) and a drain (20) in a substrate (16). A magnetic field is created in the ferromagnetic gate (12) by producing a large current between the source (18 ) and drain (20). The ... | 05/16/1989 |
