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| Number | Title | Issue Date |
| 6285240 | Low threshold MOS two phase negative charge pump A triple well charge pump comprises a first transistor connected in a diode configuration having a first channel terminal, nominally the source, coupled to a first node, and the second channel terminal, nominally the drain, coupled to its gate and to a se... | 09/04/2001 |
| 6281719 | Output pad precharge circuit for semiconductor devices An output driver for an integrated circuit performs a precharge function before internal data is available, minimizing the access time for such data. Also, the pull up and pull down circuitry used in the precharge function is separate from the output driv... | 08/28/2001 |
| 6282675 | Fault-tolerant architecture for in-circuit programming The present invention provides a method and apparatus for providing fault-tolerance for in-circuit programming systems. The invention operates by storing a minimal set of code to initialize the in-circuit programming process in a protected memory so that ... | 08/28/2001 |
| 6278649 | Bank selection structures for a memory array, including a flat cell ROM array An integrated circuit memory comprises an array of non-volatile memory cells arranged in rows and columns, and including a plurality of banks. There are a plurality of word lines along the plurality of rows in the array, and a plurality of array bit lines... | 08/21/2001 |
| 6270464 | Biopsy localization method and device A biopsy localization device made according to the invention includes a bioabsorbable element (34), such as a dehydrated collagen plug, delivered in a pre-delivery state to a soft tissue biopsy site (18) of a patient by an element delivery device (32). Th... | 08/07/2001 |
| 6269017 | Multi level mask ROM with single current path Mask ROMS with fixed code implantation and associated integrated circuits are described. An integrated circuit has a Mask ROM including: an array of memory cells including a first bank of memory cells and a second bank of memory cells, and the first bank ... | 07/31/2001 |
| 6265047 | Composite products, methods and apparatus A low-stretch, flexible composite, made of one or several sections, particularly useful for making a sail (2), includes first and second polymer films (52, 62) with discontinuous, stretch-resistant segments (16) therebetween. The segments extend generally... | 07/24/2001 |
| 6259140 | Silicide blocking process to form non-silicided regions on MOS devices A semiconductor device is formed on a substrate having an ESD region and an internal region. A protective layer is formed over a portion of the ESD region to be protected from formation of silicide and suicide is formed on portions of the Internal and ESD... | 07/10/2001 |
| 6258493 | Phase shifting circuit manufacture method and apparatus A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a singl... | 07/10/2001 |
| 6255900 | Rapid on chip voltage generation for low power integrated circuits An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost ... | 07/03/2001 |
| 6252514 | Hot-swap assembly for computers An assembly that engages a component to a computer system includes a cover adapted to retain the component and to be inserted within a chassis of the computer system. A slide movably coupled to the cover has a proximal position associated with inserting t... | 06/26/2001 |
| 6248631 | Method for forming a v-shaped floating gate The invention provides a floating gate memory cell, where the floating gate comprises a first lateral end region and a second lateral end region. A middle region is positioned towards a middle of the floating gate with respect to the first lateral end reg... | 06/19/2001 |
| 6248122 | Catheter with controlled release endoluminal prosthesis A catheter (4) includes a hollow catheter shaft (18), an inflatable balloon (36) surrounding the catheter shaft distal portion, and an expandable endoluminal prosthesis, such as a stent graft (38, 40), surrounding the balloon. The stent is typically a coi... | 06/19/2001 |
| 6238430 | Catheter assembly with controlled release endoluminal prosthesis and method for placing A catheter assembly includes a coiled endoluminal prosthesis (122, 190, 198) and a catheter (136) having at least first and second telescoping shafts (138, 140, 142). The prosthesis is releasably engaged to the distal ends (144, 146, 148) of the telescopi... | 05/29/2001 |
| 6236086 | ESD protection with buried diffusion An ESD protection circuit with buried diffusion and internal overlap coupling capacitance is used to lower trigger voltage and create a compact protection circuit area. This protection circuit can be applied to memory and logic products and can be employe... | 05/22/2001 |
| 6229732 | Regulated voltage supply circuit for inducing tunneling current in floating gate memory devices A circuit is provided for applying a negative voltage to the control gate of a floating gate memory cell and a positive voltage to the source drain or channel which comprises a positive voltage source to provide a positive voltage to the source of the cel... | 05/08/2001 |
| 6228539 | Phase shifting circuit manufacture method and apparatus A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a singl... | 05/08/2001 |
| 6221006 | Entrapping apparatus and method for use Medical devices that have a novel mechanical trap(s) on the distal end of a shaft that is used for the removal of material from the body. Further an expandable channel is included to entrap the material that aid with removal or obliteration of tissue or f... | 04/24/2001 |
| 6219290 | Memory cell sense amplifier A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path.... | 04/17/2001 |
| 6215697 | Multi-level memory cell device and method for self-converged programming A multi-level memory cell device and method for self-converged programming which includes a memory cell switchably coupled to a non-programmable reference cell (or dummy cell), the cells arranged in respective arrays. A current source voltage between the ... | 04/10/2001 |
| 6216158 | System and method using a palm sized computer to control network devices Controlling network services using palm sized computers is described. A program on the palm sized computer is used to access a registry of network services that may be available. The registry includes descriptions for various services. Each description in... | 04/10/2001 |
| 6211011 | Method for fabricating asymmetric virtual ground P-channel flash cell A memory cell having an asymmetric source and drain connection to virtual ground bit-lines providing an abrupt junction suitable for band-to-band hot electron generation and a gradual junction suitable for Fowler-Nordheim tunneling on each side of the cel... | 04/03/2001 |
| 6191724 | Short pulse microwave transceiver Harmonic techniques are employed to leverage low-cost, ordinary surface mount technology (SMT) to high microwave frequencies where tight beamforming with a small antenna makes reliable, high-accuracy pulse-echo radar systems possible. The implementation c... | 02/20/2001 |
| 6188590 | Regulator system for charge pump circuits The present invention discloses a regulator system (112) for regulating the output current and voltage (Vout) of a charge pump circuit (104). It is observed that the output current and voltage (Vout) of a charge pump circuit (104) can be regulated by vary... | 02/13/2001 |
| 6184724 | Voltage detection circuit A voltage detector circuit of a nonvolatile memory integrated circuit for determining the voltage potential of a supply voltage is provided. The voltage detector includes a first MOS device, a second MOS device, a bias circuit for adjusting the current th... | 02/06/2001 |
| 6178114 | Sensing apparatus and method for fetching multi-level cell data A reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of... | 01/23/2001 |
| 6177317 | Method of making nonvolatile memory devices having reduced resistance diffusion regions A method is described for manufacturing nonvolatile memory devices having reduced resistance diffusion regions. One embodiment of the method includes forming a multilayer structure over a substrate which includes a tunnel oxide layer, a polysilicon layer,... | 01/23/2001 |
| 6178132 | Non-volatile integrated circuit having read while write capability using one address register A non-volatile integrated circuit memory, such as a flash memory device based on floating gate transistor memory cells, with read while write capability is provided using a single address register. The integrated circuit includes at least two independent ... | 01/23/2001 |
| 6166955 | Apparatus and method for programming of flash EPROM memory An apparatus for programming selected floating gate storage transistors in a data storage device includes a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming pot... | 12/26/2000 |
| 6167556 | System for logic extraction from a layout database A system and process for logic extraction from the layout of logic blocks is described. Logic design information is extracted from a transistor level net list which is stored in a memory. The transistor level net list in turn is generated from a layout po... | 12/26/2000 |
| 6153463 | Triple plate capacitor and method for manufacturing A novel capacitor design and construction method that uses a stacked structure which is sometimes otherwise used for a so-called floating gate transistor. A first electrical contact is electrically coupled with a conductive region formed in the substrate ... | 11/28/2000 |
| 6154390 | Sensing apparatus and method for fetching multi-level cell data A reading circuit for a multibit memory cell in a memory array, the memory cell having a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages corresponding respectively to one of four states of... | 11/28/2000 |
| 6151657 | Processor with embedded in-circuit programming structures An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself, as well as other software stored on the chip. The architecture is based on a microcontroller on an in... | 11/21/2000 |
| 6140682 | Self protected stacked NMOS with non-silicided region to protect mixed-voltage I/O pad from ESD damage A self-protected output driver for an integrated circuit utilizing cascode configured MOSFET transistors is formed in a single active region, allowing a smaller layout area without sacrificing performance. Furthermore, the driver is laid out according to ... | 10/31/2000 |
| 6137438 | Precision short-range pulse-echo systems with automatic pulse detectors An equivalent time pulse-echo radar or other pulse-echo system employs a transmit reference sampler collocated with the transmitter to provide a transmit reference pulse, which initiates a pulse width modulated (PWM) pulse. A receive sampler connected to ... | 10/24/2000 |
| 6130452 | Virtual ground flash cell with asymmetrically placed source and drain and method of fabrication A memory cell having asymmetrically placed source and drain diffusions which allows programming and erasure to be obtained across one of the source or drain diffusions which extends furthest beneath the floating gate while minimizing electron tunneling at... | 10/10/2000 |
| 6130134 | Method for forming asymmetric flash EEPROM with a pocket to focus electron injections A memory cell having an asymmetric source and drain connection to virtual ground bit-lines. A main diffusion, adjacent the drain and displaced from the source, allows Fowler-Nordheim (FN) tunneling erasure on the drain side of the floating gate. A pocket ... | 10/10/2000 |
| 6121092 | Silicide blocking process to form non-silicided regions on MOS devices A semiconductor device is formed on a substrate having an ESD region and an internal region. A protective layer is formed over a portion of the ESD region to be protected from formation of silicide and silicide is formed on portions of the Internal and ES... | 09/19/2000 |
| 6119226 | Memory supporting multiple address protocols The present invention provides a new memory device for storage of boot code for microprocessors which boot to either the top or bottom of a memory map on power-up. The device includes a memory array, a first block, and decoders. The first block is defined... | 09/12/2000 |
| 6104665 | Enhanced word line driver to reduce gate capacitance for low voltage applications An enhanced word line driver circuit suitable for use on integrated circuits such as flash memory devices with voltage boosting includes a load reduction circuit. In response to a boosted voltage, the load reduction circuit decouples a gate capacitance lo... | 08/15/2000 |
