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| Number | Title | Issue Date |
| 8068370 | Floating gate memory device with interpoly charge trapping structure A charge trapping floating gate is described with asymmetric tunneling barriers. The memory cell includes a source region and a drain region separated by a channel region. A first tunneling barrier structure is disposed above the channel region. A floating gate is d... | 11/29/2011 |
| 7209500 | Stimulated Brillouin scattering mirror system, high power laser and laser peening method and system using same A laser system, such as a master oscillator/power amplifier system, comprises a gain medium and a stimulated Brillouin scattering SBS mirror system. The SBS mirror system includes an in situ filtered SBS medium that comprises a compound having a small negative non-l... | 04/24/2007 |
| 7199728 | Communication system with low power, DC-balanced serial link A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set... | 04/03/2007 |
| 7192834 | LDMOS device and method of fabrication of LDMOS device A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a ... | 03/20/2007 |
| 7190614 | Operation scheme for programming charge trapping non-volatile memory A circuit and method for self-converging programming of a charge storage memory cell, such as NROM or floating gate flash. The method includes determining a data value from one of more than two data values to be stored in the memory cell, and applying a gate voltage... | 03/13/2007 |
| 7169515 | Phase conflict resolution for photolithographic masks A photolithographic mask used for defining a layer in an integrated circuit, or other work piece, where the layer comprises a pattern including a plurality of features to be implemented with phase shifting in phase shift regions is laid out including for patterns co... | 01/30/2007 |
| 7164603 | Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory A memory cell with a charge trapping structure has multiple bias arrangements. Multiple cycles of applying the bias arrangements lowering and raising a threshold voltage of the memory cell leave a distribution of charge in the charge trapping layer. The charge inter... | 01/16/2007 |
| 7147654 | Treatment Site Cooling System of Skin Disorders A method and apparatus for treating skin disorders includes a source of pulsed near black body electromagnetic energy and a means of delivering this energy to a treatment site. A means for cooling the treatment site is described. The number of pulses and intensity o... | 12/12/2006 |
| 7148105 | Method for forming polysilicon floating gate A floating gate memory cell comprises a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. The depositi... | 12/12/2006 |
| 7142246 | Apparatus and method for de-interlacing video, including 3:2 pulldown video An output stream of the de-interlaced image frames is produced from an incoming stream of interlaced image fields, where the interlaced image fields include complementary pairs of fields, which together comprise a frame. An input buffer includes field buffers storin... | 11/28/2006 |
| 7142583 | Receiver with plural detecting processors A receiver for detecting and recovering data from received data bearing radio signal samples comprises first and second detecting processors. Each of the detecting processors comprises a data store operable to store a predetermined number of the signal samples, an e... | 11/28/2006 |
| 7132203 | Phase shift masking for complex patterns with proximity adjustments Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase sh... | 11/07/2006 |
| 7130222 | Nonvolatile memory with program while program verify A page mode program sequence is described that includes first and second bias applying cycles. In the first cycle, a program bias is applied to a first part of a page of memory cells, while a program verify bias is applied to, and data is sensed from, a second part ... | 10/31/2006 |
| 7112518 | Method and apparatus for cutting devices from substrates A method and system for cutting a wafer comprising a semiconductor substrate attached to an array of integrated devices includes placing the wafer on a stage such as a movable X-Y stage including a vacuum chuck having a porous mounting surface, and securing the wafe... | 09/26/2006 |
| 7110174 | Relay telescope for high power laser alignment system A laser system includes an optical path having an intracavity relay telescope with a telescope focal point for imaging an output of the gain medium between an image location at or near the gain medium and an image location at or near an output coupler for the laser ... | 09/19/2006 |
| 7110171 | Relay telescope including baffle, and high power laser amplifier utilizing the same A laser system includes an optical path having an intracavity relay telescope with a telescope focal point for imaging an output of the gain medium between an image location at or near the gain medium and an image location at or near an output coupler for the laser ... | 09/19/2006 |
| 7106625 | Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes two charge trapping locations beneath each of all or some of the gates in ... | 09/12/2006 |
| 7095789 | Communication channel calibration for drift conditions A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its p... | 08/22/2006 |
| 7089439 | Architecture and method for output clock generation on a high speed memory device An output clock for a memory device having a read latency more than one clock cycle includes a clock generator at a central location on the device. A clock channel couples the clock generator to output structures. A timing path emulates the address/data paths in the... | 08/08/2006 |
| 7088270 | Low power, DC-balanced serial link A receiver for a data communication system which comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence... | 08/08/2006 |
| 7088276 | Enhanced data converters using compression and decompression An enhancement that reduces the digital interface rate of analog-to-digital (A/D) and digital-to-analog (D/A) converters through the use of compression and decompression is described. The present invention improves A/D converters by compressing the sampled version o... | 08/08/2006 |
| 7088630 | Circuit and method for high speed sensing A circuit and method for sensing a difference between a first signal, such as a signal from the source side of a memory cell, and a second signal, such as a signal from a reference dummy cell, includes developing first and second voltages respectively in response to... | 08/08/2006 |
| 7082061 | Memory array with low power bit line precharge An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupl... | 07/25/2006 |
| 7082069 | Memory array with fast bit line precharge An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Precharge transistors are c... | 07/25/2006 |
| 7071852 | Enhanced test and measurement instruments using compression and decompression An enhancement that improves the performance of test and measurement equipment such as digital oscilloscopes and arbitrary waveform generators through the use of compression and decompression is described. The present invention is particularly effective for compress... | 07/04/2006 |
| 7063694 | Method and system for photoselective vaporization for gynecological treatments A method for photoselective vaporization of uterine tissue includes delivering laser radiation to the treatment area on the tissue, via an optical fiber for example, wherein the laser radiation has a wavelength and irradiance in the treatment area on the surface of ... | 06/20/2006 |
| 7060594 | Memory device and method of manufacturing including deuterated oxynitride charge trapping structure A method for manufacturing a charge storage stack including a bottom dielectric layer, a charge trapping structure on the bottom dielectric layer, and a top dielectric layer, each comprising silicon oxynitride, are formed using reactant gases that comprise hydrogen,... | 06/13/2006 |
| 7061406 | Low power, DC-balanced serial link transmitter A transmitter for a data communication system that comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequen... | 06/13/2006 |
| 7052976 | Method and apparatus for cutting devices from conductive substrates secured during cutting by vacuum pressure A method and system for cutting a wafer comprising a conductive substrate attached to an array of integrated devices includes placing the wafer on a stage such as a movable X-Y stage including a vacuum chuck having a porous mounting surface, and securing the wafer d... | 05/30/2006 |
| 7033856 | Spacer chalcogenide memory method The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings. ... | 04/25/2006 |
| 7009533 | Adaptive compression and decompression of bandlimited signals An efficient method for compressing sampled analog signals in real time, without loss, or at a user-specified rate or distortion level, is described. The present invention is particularly effective for compressing and decompressing high-speed, bandlimited analog sig... | 03/07/2006 |
| 7006522 | System and method for alert generation using network interface A system which provides for generation of alert packets using network interfaces. The alert packets are downloaded into a network interface, for example during a transition from an OS-present state to an OS-absent state. The alert packets are provided with control f... | 02/28/2006 |
| 6992983 | Bandwidth detection in a heterogeneous network with parallel and proxy modes Effective bandwidth of a communication link is determined in a heterogeneous, packet switched network between a source and a destination, where effective bandwidth is defined as the actual available bandwidth between the server and the client, minus the overhead of ... | 01/31/2006 |
| 6986956 | Method of coating smooth electroless nickel on magnetic memory disks and related memory devices A method of manufacture of thin film magnetic disks and other useful articles of similar planar geometry in which a non-magnetic layer is first deposited on one or both sides of the disk or article substrate to mask chemical and mechanically induced heterogeneities ... | 01/17/2006 |
| 6979519 | Phase shifting circuit manufacture method and apparatus A method for manufacturing integrated circuits using opaque field, phase shift masking. One embodiment of the invention includes using a two mask process. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phas... | 12/27/2005 |
| 6977030 | Method of coating smooth electroless nickel on magnetic memory disks and related memory devices A method of manufacture of thin film magnetic disks and other useful articles of similar planar geometry in which a non-magnetic layer is first deposited on one or both sides of the disk or article substrate to mask chemical and mechanically induced heterogeneities ... | 12/20/2005 |
| 6970921 | Network interface supporting virtual paths for quality of service A plurality of virtual paths in a network interface between a host port and a network port are managed according to respective priorities. Thus, multiple levels of quality of service are supported through a single physical network port. Variant processes are applied... | 11/29/2005 |
| 6961862 | Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logi... | 11/01/2005 |
| 6953146 | Low-temperature flux for soldering nickel-titanium alloys and other metals A low-temperature flux is described which dissolves the refractory oxide layer from a shape memory alloy containing both nickel and titanium, such as Nitinol, and from other metals like stainless steel. The flux is particularly useful for preparing shape memory allo... | 10/11/2005 |
| 6934263 | Spanning tree with protocol for bypassing port state transition timers Mechanisms for use on designated ports in spanning tree protocol entities allow such ports to transition to a forwarding state on the basis of actual communication delays between neighboring bridges, rather than upon expiration of forwarding delay timers. The logic ... | 08/23/2005 |
