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| Number | Title | Issue Date |
| 7335610 | Ultraviolet blocking layer Semiconductor structures and methods of fabricating semiconductor structures are disclosed. The method comprises the steps of: providing an initial semiconductor structure; forming a non-silicon layer overlying the initial semiconductor structure, the non-silicon la... | 02/26/2008 |
| 7238994 | Thin film plate phase change ram circuit and manufacturing method A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes elec... | 07/03/2007 |
| 7237145 | Fault-tolerant architecture for in-circuit programming The present invention provides a method and apparatus for providing fault-tolerance for in-circuit programming systems. The invention operates by storing a minimal set of code to initialize the in-circuit programming process in a protected memory so that if the in-c... | 06/26/2007 |
| 7209406 | Memory device with rapid word line switch A memory device includes an array of storage cells, multiple words lines, where each word line corresponds to a row in the array of storage cells, and multiple bit lines, where each bit line corresponds to a column in the array of storage cells. The device further i... | 04/24/2007 |
| 7209390 | Operation scheme for spectrum shift in charge trapping non-volatile memory A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in ... | 04/24/2007 |
| 7209389 | Trap read only non-volatile memory (TROM) A Trap Read Only Memory (TROM) architecture employs a NAND-type array structure configured as a read-only memory that is programmed only one time. The memory cells in the array comprise a gate terminal, a first channel terminal (source/drain), a second channel termi... | 04/24/2007 |
| 7209386 | Charge trapping non-volatile memory and method for gate-by-gate erase for same A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath gates in the plurality of gates. Circuit... | 04/24/2007 |
| 7188314 | System and method for user authentication interface A graphical user interface supports an interactive client-server authentication based on Random Partial Pattern Recognition algorithm (RPPR). In RPPR, an ordered set of data fields is stored for a client to be authenticated in secure memory on the server side. A gra... | 03/06/2007 |
| 7187527 | Electrostatic discharge conduction device and mixed power integrated circuits using same A device for connection between supply buses in mixed power integrated circuits includes a diode in series with a transistor with an active p-ring in a semiconductor substrate. The active p-ring surrounds the source and drain of the transistor with a conductive regi... | 03/06/2007 |
| 7181297 | System and method for delivering customized audio data A method for providing customized audio data products that includes the steps of (1) storing a machine readable hearing profile for a customer, (2) accepting via a data input device or data network for example, machine readable orders from the customer for a particu... | 02/20/2007 |
| 7180918 | Self-seeded single-frequency solid-state ring laser and system using same A method of operating a laser to obtain an output pulse having a single wavelength, comprises inducing an intracavity loss into a laser resonator having an amount that prevents oscillation during a time that energy from the pump source is being stored in the gain me... | 02/20/2007 |
| 7180123 | Method for programming programmable eraseless memory A method for programming a memory cell is based on applying stress to a memory cell, comprising a first electrode, a second electrode and an inter-electrode layer, to induce a progressive change in a property of the inter-electrode layer. The method includes a verif... | 02/20/2007 |
| 7177320 | Transfer of data in a telecommunications system A telecommunications system comprises a transmitter within the central terminal for sending a data message destined for a particular subscriber terminal over communication channels as a number of data blocks. A frame generator is provided within the central terminal... | 02/13/2007 |
| 7169688 | Method and apparatus for cutting devices from substrates A method and system for cutting a wafer comprising a semiconductor substrate attached to an array of integrated devices includes placing the wafer on a stage such as a movable X-Y stage including a vacuum chuck having a porous mounting surface, and securing the wafe... | 01/30/2007 |
| 7159136 | Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logi... | 01/02/2007 |
| 7158420 | Inversion bit line, charge trapping non-volatile memory and method of operating same A charge trapping memory device in which a field induced inversion layer is used to replace the source and drain implants. The memory cell are adapted to store two bits, one on the left side and one on the right side of the charge trapping structure. A positive thre... | 01/02/2007 |
| 7158411 | Integrated code and data flash memory A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise ch... | 01/02/2007 |
| 7151694 | Integrated circuit memory with fast page mode verify A method for operating an integrated circuit memory device includes applying a verify procedure in which the page of data and one or more bits from a set of replacement cells are matched with a pattern in parallel to indicate a verify result, where the page of data ... | 12/19/2006 |
| 7151692 | Operation scheme for programming charge trapping non-volatile memory A circuit and method for self-converging programming of a charge storage memory cell, such as NROM or floating gate flash. The method includes determining a data value from one of more than two data values to be stored in the memory cell, and applying a gate voltage... | 12/19/2006 |
| 7133313 | Operation scheme with charge balancing for charge trapping non-volatile memory A memory cell with a charge trapping structure has multiple bias arrangements. Multiple cycles of applying the bias arrangements lowering and raising a threshold voltage of the memory cell leave a distribution of charge in the charge trapping layer. The charge inter... | 11/07/2006 |
| 7132350 | Method for manufacturing a programmable eraseless memory A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in... | 11/07/2006 |
| 7120059 | Memory array including multiple-gate charge trapping non-volatile cells An array of multiple-gate memory cells includes sectors. The sectors include at least one row of multiple-gate memory cells. The multiple-gate memory cells comprise a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge ... | 10/10/2006 |
| 7075828 | Operation scheme with charge balancing erase for charge trapping non-volatile memory A method of operating a memory cell comprises applying a first procedure (typically erase) to establish a low threshold state including a first bias arrangement causing reduction in negative charge in the charge trapping structure, and a second bias arrangement tend... | 07/11/2006 |
| 7073067 | Authentication system and method based upon random partial digitized path recognition An authentication server provides a clue to a client indicating a random partial subset of a full pattern that characterizes a full digitized path on a frame of reference, and the client enters a data to fulfill an authentication factor suggested by the clue. The fu... | 07/04/2006 |
| 7072355 | Periodic interface calibration for high speed communication A high-speed communication interface manages a parallel bus having N bus lines. N+1 communication lines are established. A maintenance operation is performed on one of the N+1 communication lines, while N of the N+1 communication lines is available for data from the... | 07/04/2006 |
| 7071992 | Methods and apparatus for bridging different video formats A video format bridge employs a plurality of techniques to insure that the line buffer does not suffer underflow or overflow conditions, and that the output frame rate matches the input frame rate. The bridge handles the problem of residue lines, addresses fluctuati... | 07/04/2006 |
| 7067374 | Manufacturing methods and structures of memory device Dual spacer structures are fabricated such that sidewall spacers in a cell region are thinner than sidewall spacers in a periphery region. The fabricating method of memory includes forming a stop layer over the first semiconductor feature and the second semiconducto... | 06/27/2006 |
