Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 4997780 | Method of making CMOS integrated devices in seeded islands The structure of a pair of concentrically disposed field effect transistors responsive to a common gate electrode, and a process for the fabrication thereof. In one form, a dielectric region is surrounded by an active region of monocrystalline silicon and... | 03/05/1991 |
| 4987551 | Apparatus for creating a cursor pattern by strips related to individual scan lines An architecture for generating a hardware cursor in the context of a bit mapped video display system operable from a frame buffer with non-displayed but addressable memory space. A segment of the non-displayed memory is loaded with cursor outline and patt... | 01/22/1991 |
| 4928160 | Gate isolated base cell structure with off-grid gate polysilicon pattern A CMOS gate isolated gate array configured with a single polysilicon layer and preferably two metallization layers, wherein the cell pitch is equal to the first and second metallization pitches by referencing the metallization layers, contacts and vias to... | 05/22/1990 |
| 4923563 | Semiconductor field oxide formation process using a sealing sidewall of consumable nitride An integrataed circuit fabrication process for creating field oxide regions having substantially no bird's beak, a relatively planar concluding surface, substantially no stress induced dislocations at the edges of the active regions, and a substantial abs... | 05/08/1990 |
| 4920344 | Digitally compensated multiplying digital to analog converter A multiplying digital to analog converter using ladder networks and binary weighted load compensation to allow integration and video frequency operation. In one form, the circuit is configured from field effect transistors which incorporate by virtue of t... | 04/24/1990 |
| 4918587 | Prefetch circuit for a computer memory subject to consecutive addressing A computer memory prefetch architecture for accelerating the rate at which data can be accessed from memory and transmitted to a processor when successive addresses are numerically consecutive. Upon the identification of a consecutive address sequence, th... | 04/17/1990 |
| 4893116 | Logical drawing and transparency circuits for bit mapped video display controllers An interface controller, situated between a graphics controller and a memory array in a color video display system operable in a read-modify-write mode, configured to detect a select transparency color in whole or in part and to respond by selectively cha... | 01/09/1990 |
| 4890010 | Matched current source serial bus driver A matched current source bus driver circuit providing time and magnitude matched currents as sources and sinks to a pair of serial bus lines. A reference current path is established in transistors which are structurally mirrored to the devices sourcing an... | 12/26/1989 |
| 4880997 | Low noise output buffer circuit A buffer circuit with controlled output switching rate suitable to suppress ground or power supply line voltage spikes attributable to current surges. The voltage driving the gate electrode of the selected CMOS inverter output transistor is controlled in ... | 11/14/1989 |
| 4876582 | Crystallized silicon-on-insulator nonvolatile memory device Disclosed is a nonvolatile memory device which utilizes a laser beam recrystallized silicon layer having source-channel-drain regions. Underlying the recrystallized layer and separated therefrom by a memory dielectric is a gate in alignment with the sourc... | 10/24/1989 |
| 4875151 | Two transistor full wave rectifier An integrated circuit two transistor full wave rectifier suitable for fabrication in a CMOS, NMOS or PMOS process and characterized by a high level of integration based upon shared utilization of doped regions. In one form, the full wave rectifier is conf... | 10/17/1989 |
| 4874713 | Method of making asymmetrically optimized CMOS field effect transistors A process for forming an asymmetrically structured pair of CMOS field effect transistors having feature refinements matched to the individual idiosyncrasies of the p-channel and n-channel transistors. Complementary transistors are formed using a single ph... | 10/17/1989 |
