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| Number | Title | Issue Date |
| 8112555 | Peripheral adapter interrupt frequency control by estimating processor load at the peripheral adapter Interrupt frequency control by estimating processor load in the peripheral adapter provides adaptive interrupt latency to improve performance in a processing system. A mathematical function of the depth of one or more queues of the adapter is compared to its histori... | 02/07/2012 |
| 8091059 | Method for diffusion based cell placement migration A method for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to cont... | 01/03/2012 |
| 8060699 | Spiral cache memory and method of operating a spiral cache A memory provides reduction in access latency for frequently-accessed values by self-organizing to always move a requested value to a front-most central storage element of a spiral. The occupant of the central location is swapped backward, which continues backward t... | 11/15/2011 |
| 8051213 | Method for server-directed packet forwarding by a network controller based on a packet buffer threshold A network controller improves load-balancing within a network system without requiring an intelligent switch having TCP splicing capability. The network controller forwards connections in response to directives from the connected server, permitting connection splici... | 11/01/2011 |
| 8008902 | Hysteretic buck converter having dynamic thresholds A hysteretic buck converter provides improved regulation control, in particular for buck converter standby operation. A comparison circuit compares the output voltage of the buck converter to a waveform that is generated from an indication of the output current of t... | 08/30/2011 |
| 8008898 | Switching regulator with boosted auxiliary winding supply A boosted auxiliary winding power supply for a switched-power converter circuit provides operating voltage for control and other circuits early in the start-up phase of converter operation. A boost circuit has an input coupled to the auxiliary winding to boost the v... | 08/30/2011 |
| 7992023 | Method and system for managing peripheral connection wakeup in a processing system supporting multiple virtual machines A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The p... | 08/02/2011 |
| 7925901 | Method and system for estimating processor utilization from power measurements A method and system for estimating processor utilization from power measurements provides an estimate of processor utilization that can be computed outside of the processor and operating system. Measurements of the processor power consumption are gathered over short... | 04/12/2011 |
| 7903825 | Personal audio playback device having gain control responsive to environmental sounds A personal audio playback device having gain control responsive to environmental sounds provides for improved enjoyment of program material played back through headphones, while further providing features for personal safety and communications with others. A microph... | 03/08/2011 |
| 7835373 | Method and apparatus for buffer linking in bridged networks A computer implemented method and apparatus are provided for transferring data in a logical partitioned data processing system. A receiving adapter receives data from a network. The receiving adapter transfers the data to a pre-mapped buffer if the data is to be sen... | 11/16/2010 |
| 7821796 | Reference plane voids with strip segment for improving transmission line integrity over vias Reference plane voids with a strip segment for improving transmission line integrity over vias permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or be... | 10/26/2010 |
| 7752470 | Method and system for power management including device controller-based device use evaluation and power-state control A method and system for power management including device controller-based device use evaluation and power-state control provides improved performance in a power-managed processing system. Per-device usage information is measured and evaluated during process executi... | 07/06/2010 |
| 7752075 | Method and system for auction or sales of deliverable prepared food via the internet A method and system for auctioning items via the Internet permit customers to bid on items and others to bid after delivery has been scheduled, and optionally commenced, to a previous bidder. A bid increment is set according to a geographic location of the new bidde... | 07/06/2010 |
| 7748748 | Method and system for generating and authenticating documents having stored electrostatic pattern information A method and apparatus for generating and authenticating documents having stored electrostatic pattern information provides security with respect to the authenticity of documents. A liquid medium including a plurality of electrostatic monopoles is applied to the sur... | 07/06/2010 |
| 7746988 | Method, system and telephone answering device for processing control scripts attached to voice messages A method, system and telephone answering device for processing control scripts attached to voice messages provides a mechanism by which a caller can leave an interactive list of contact information. The scripts provide for control of a display and input responses fr... | 06/29/2010 |
| 7696787 | Signal history controlled slew-rate transmission method and bus interface transmitter A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis... | 04/13/2010 |
| 7659749 | Pulsed dynamic logic environment metric measurement circuit A pulsed dynamic logic environment metric measurement circuit provides self-referenced, low area/cost and low power measurement of circuit environment metrics, such as supply voltage. A cascade of dynamic logic stages is clocked with a pulse having a width substanti... | 02/09/2010 |
| 7646082 | Multi-layer circuit substrate and method having improved transmission line integrity and increased routing density A multi-layer circuit substrate and method having improved transmission line integrity and increased routing density uses a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impe... | 01/12/2010 |
| 7636556 | Digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of p... | 12/22/2009 |
| 7626360 | Charge-pump biased battery protection circuit A charge-pump biased battery protection circuit provides improved efficiency, reduced power dissipation, and reduced complexity in battery powered circuits. A charge pump is utilized to bias the gate of a single pass transistor such that the voltage between the pass... | 12/01/2009 |
| 7620510 | Pulsed ring oscillator circuit for storage cell read timing evaluation A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator a... | 11/17/2009 |
| 7597094 | Compound bow maintenance press and method for compressing a compound bow from the bow limb ends A compound bow maintenance press and method for compressing a compound bow from the bow limb ends provides a shop-installable bow press that prevents damage to the bow riser and limbs during service. The press contacts the bow only at the ends of the bow limbs and c... | 10/06/2009 |
| 7570118 | Thermal overload protection circuit and method for protecting switching power amplifier circuits A thermal overload protection circuit and method for protecting switching power amplifier circuits provides protection against latch-up and other failures due to energy returned from an inductive load when the amplifier output is disabled in response to a thermal ov... | 08/04/2009 |
| 7558358 | Method and apparatus for generating a clock signal according to an ideal frequency ratio A method and apparatus for generating a clock signal according to an ideal frequency ratio provides flexible and reduced frequency error clock generation. A ratio control number is specified or is determined from a phase-frequency comparison of the clock signal to a... | 07/07/2009 |
| 7557661 | Direct digital synthesis (DDS) hybrid phase-lock loop for low-jitter synchronization A direct digital synthesis (DDS) hybrid phase-lock loop for low-jitter synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level. A DDS circuit provides a clock output and has an input for receiving a... | 07/07/2009 |
| 7554409 | Over-current protection circuit and method for protecting switching power amplifier circuits An over-current protection circuit protection circuit and method for protecting switching power amplifier circuits provides protection against latch-up and other failures due to energy returned from an inductive load when one or more transistors in the amplifier out... | 06/30/2009 |
| 7552413 | System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is part... | 06/23/2009 |
| 7552040 | Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit... | 06/23/2009 |
| 7548823 | Correction of delay-based metric measurements using delay circuits having differing metric sensitivities Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measu... | 06/16/2009 |
| 7545690 | Method for evaluating memory cell performance A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complem... | 06/09/2009 |
| 7539841 | Machine memory power and availability management in a processing system supporting multiple virtual machines A processing system and computer program provides memory power management and memory failure management in large scale systems. Upon a decision to take a memory module off-line or place the module in an increased-latency state for power management, or upon a notific... | 05/26/2009 |
| 7536577 | Calibration technique for power measurement and management over multiple time frames A calibration technique provides for precision calibration of system power measurement. The calibration technique uses a precision reference resistor and voltage reference controlled current source to introduce a voltage drop from the input side of a power supply se... | 05/19/2009 |
| 7535396 | Digital-to-analog converter (DAC) having filter sections with differing polarity A digital-to-analog converter (DAC) having filter sections with differing polarity provides a low-noise, low area bipolar output solution in delta-sigma modulator based DACs. A shift register receives an input bit-stream and provides a series of tap outputs that are... | 05/19/2009 |
| 7533003 | Weighted event counting system and method for processor performance measurements A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provide... | 05/12/2009 |
| 7515076 | Method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog-to-digital converter (ADC) A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and... | 04/07/2009 |
| 7477178 | Power-optimized analog-to-digital converter (ADC) input circuit A power-optimized analog-to-digital converter (ADC) input circuit provides for optimized power consumption versus performance. The first amplifier stage of the ADC is provided by a plurality of amplifiers that are selectably enabled to provide a particular bandwidth... | 01/13/2009 |
| 7471340 | Video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal A video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal reduces the buffer size required to compensate for line-to-line variations in an unstable video source. A video signal is sampled at a predetermined rate and de... | 12/30/2008 |
| 7424691 | Method for verifying performance of an array by simulating operation of edge cells in a full array model A method for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjecte... | 09/09/2008 |
| 7414904 | Method for evaluating storage cell design using a wordline timing and cell access detection circuit A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or... | 08/19/2008 |
| 7411534 | Analog-to-digital converter (ADC) having integrator dither injection and quantizer output compensation An analog-to-digital converter (ADC) having integrator dither injection and quantizer output compensation reduces the probability of unchanging code sequences that occur when the input signal and feedback signal are equal and thus no quantizer output change occurs. ... | 08/12/2008 |
