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| Number | Title | Issue Date |
| 8185462 | Stochastic control system and method for multi-period consumption The present invention relates to dynamic optimization of system control over time. The need for dynamic optimization arises in many settings, as diverse as solar car power consumption during a multi-day race and retirement portfolio management. We disclose a reformu... | 05/22/2012 |
| D660138 | Stopper clip | 05/22/2012 |
| 8180514 | Autonomous agriculture platform guidance system A guidance system for an agriculture platform that is capable of making decisions concerning the platforms direction and velocity regarding the pathway the platform is moving along as well as obstacles in the path of the platform, is provided. The autonomous agricul... | 05/15/2012 |
| 8178405 | Resistor random access memory cell device A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory mat... | 05/15/2012 |
| 8178387 | Methods for reducing recrystallization time for a phase change material A method for reducing recrystallization time for a phase change material of a memory cell element in conjunction with the manufacture of a memory cell device can be carried out as follows. A phase change material, a buffer layer material and a cladding layer materia... | 05/15/2012 |
| 8178386 | Phase change memory cell array with self-converged bottom electrode and method for manufacturing An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are... | 05/15/2012 |
| 8173987 | Integrated circuit 3D phase change memory array and manufacturing method A 3D phase change memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable phase change memory element and a thresh... | 05/08/2012 |
| 8171396 | Method and apparatus for declarative updating of self-describing, structured documents The present invention includes a method and device for updating a self-describing, structured document. A further aspect of the present invention is enabling client-based modification of the document. Additional aspects of the present invention are described in the ... | 05/01/2012 |
| 8170121 | H.264/AVC based approach to scalable video compression A scalable video compression method and apparatus for encoding an input frame sequence having temporally sequential frames includes partitioning each of the frames of the input frame sequence into a top field and a bottom field to form a base layer sequence of field... | 05/01/2012 |
| 8169835 | Charge trapping memory cell having bandgap engineered tunneling structure with oxynitride isolation layer A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer compris... | 05/01/2012 |
| 8168538 | Buried silicide structure and method for making Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of tre... | 05/01/2012 |
| 8164146 | Substrate symmetrical silicide source/drain surrounding gate transistor Field effect transistors described herein include first and second terminals vertically separated by a channel region. The first and second terminals comprise first and second silicide elements respectively. The first silicide element prevents the migration of carri... | 04/24/2012 |
| 8160351 | Method and apparatus for mura detection and metrology The invention addresses the lack of comprehensive and quantitative methods for measurements of unwanted visual “mura” effects in displays and image sensors. Mura is generated by errors that are significantly smaller than what is needed for the function of the de... | 04/17/2012 |
| 8158965 | Heating center PCRAM structure and methods for making Memory devices are described along with manufacturing methods. A memory device as described herein includes a bottom electrode and a first phase change layer comprising a first phase change material on the bottom electrode. A resistive heater comprising a heater mat... | 04/17/2012 |
| 8158963 | Programmable resistive RAM and manufacturing method Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size. ... | 04/17/2012 |
| 8157738 | Ultrasound signal compression A method and an apparatus for an ultrasound system provide compression of ultrasound signal samples after analog to digital conversion and before beamforming. The analog ultrasound signals received from an array of ultrasound transducer elements are digitally sample... | 04/17/2012 |
| 8156085 | Java object cache server for databases A cache server is provided in a network for storing Java objects for retrieval by one or multiple application servers. Application server(s) are configured to request an object from the cache server, rather than requesting the Java object directly from a database, s... | 04/10/2012 |
| 8154128 | 3D integrated circuit layer interconnect A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is pro... | 04/10/2012 |
| 8153491 | Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between... | 04/10/2012 |
| 8151236 | Steiner tree based approach for polygon fracturing Roughly described, a method for mask data preparation is described, for use with a preliminary mask layout that includes a starting polygon, the vertices of the starting polygon including I-points (vertices of the starting polygon having an interior angle greater th... | 04/03/2012 |
| 8151022 | Compression and storage of projection data in a rotatable part of a computed tomography system A method and apparatus compress projection data and store the compressed projection data in a rotatable part that is mounted for rotation within a stationary part. The data acquisition source, compressor and storage device are connected to the rotatable part. The co... | 04/03/2012 |
| 8149628 | Operating method of non-volatile memory device A non-volatile memory device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the... | 04/03/2012 |
| 8149627 | Current sink system based on sample and hold for source side sensing Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current ... | 04/03/2012 |
| 8149624 | Method and apparatus for reducing read disturb in memory Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage. ... | 04/03/2012 |
| 8146125 | Computerized device and method for analyzing signals in a multimedia over coax alliance (MOCA) network and similar TDM / encrypted networks The present invention relates to testing signals on a coaxial home network that carries a digital video signal. It has direct application to testing so-called Multimedia over Coax Alliance (MoCA) standards-compliant networks and applies to similar networks. In one m... | 03/27/2012 |
| 8144792 | Communication channel calibration for drift conditions A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its p... | 03/27/2012 |
| 8144307 | Image forming method and apparatus An array of phase-shifting micro-mechanical elements are used in a method and device for patterning a workpiece, for exposing a radiation sensitive layer on a workpiece such as a mask or a device substrate. The phase-shifting micro-mechanical elements are individual... | 03/27/2012 |
| 8143612 | Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lith... | 03/27/2012 |
| 8143089 | Self-align planerized bottom electrode phase change memory and manufacturing method A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chem... | 03/27/2012 |
| 8139393 | Method and apparatus for non-volatile multi-bit memory A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A conne... | 03/20/2012 |
| 8138028 | Method for manufacturing a phase change memory device with pillar bottom electrode A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode m... | 03/20/2012 |
| 8134865 | Operating method of electrical pulse voltage for RRAM application Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the me... | 03/13/2012 |
| 8134857 | Methods for high speed reading operation of phase change memory and device employing same Phase change based memory devices and methods for operating described herein overcome the performance limitations of slow set speeds and long recovery times commonly associated with phase change memory devices, enabling high speed operation and extending their usefu... | 03/13/2012 |
| 8134139 | Programmable metallization cell with ion buffer layer A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ion... | 03/13/2012 |
| 8133759 | Leadframe A leadframe includes a die paddle and leads, in which the back side of the die paddle has a fillister. The fillister defines a rim surrounding a recess, and the recess accommodates protrusion of fusible material. Also, a package includes such a leadframe. Also, a me... | 03/13/2012 |
| 8131895 | Interrupt management for multiple event queues Method of managing interaction between a host subsystem and a peripheral device. Roughly described, the peripheral device writes an event into an individual event queue, and in conjunction therewith, also writes a wakeup event into an intermediary event queue. The w... | 03/06/2012 |
| 8130760 | Session initiation and maintenance while roaming The technology disclosed addresses initiation of peer-to-peer media exchange sessions, with traversal of NAT and firewall devices, in a manner adapted to roaming. In particular, involves preliminary determination of NAT/firewall topology, which reduces latency at in... | 03/06/2012 |
| 8129706 | Structures and methods of a bistable resistive random access memory Structures and methods to form a bistable resistive random access memory for reducing the amount of heat dissipation from electrodes by confining a heating region in the memory cell device are described. The heating region is confined in a kernel comprising a progra... | 03/06/2012 |
| 8126898 | Method and system for generating scored recommendations based on scored references A computer method includes receiving a query from a user system; searching a plurality of data objects of a first type for data objects that substantially match the query; generating a first-relevance score for each data object of the second type that is associated ... | 02/28/2012 |
| 8121803 | Communication channel calibration using feedback A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal o... | 02/21/2012 |
