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| Number | Title | Issue Date |
| 5458999 | Interferometric phase shifting method for high resolution microlithography A phase shifting method uses a special interferometer in which the illuminating beam is divided into two or more components and the mask is irradiated from both sides. The pattern to be transferred onto the wafer (the mask) is generated on an optically tr... | 10/17/1995 |
| 5237460 | Storage of compressed data on random access storage devices A random-access type storage device such as a hard disk or semiconductor memory is formatted to provide multiple partitions of varying block size. The data to be stored is in blocks of fixed size, and these blocks are compressed if the compressed size fit... | 08/17/1993 |
| 4883543 | Shielding for implant in manufacture of dynamic memory A method for making semiconductor devices such as dynamic read/write memory cell arrays of the one-transistor N- channel silicon gate type employs an ion implant of high dosage to produce N+ source/drain regions. The transistor and capacitor gates are in ... | 11/28/1989 |
| 4870555 | High-efficiency DC-to-DC power supply with synchronous rectification A synchronous rectifier power supply circuit has a pair of power MOS transistors connected in series with the primary and secondary of a transformer, respectively, and another power MOS transistor connected across an inductive load on the secondary side. ... | 09/26/1989 |
| 4816425 | Polycide process for integrated circuits A process for making a semiconductor integrated circuit which has electrodes, contacts and interconnects composed of a multilayer structure including a layer of polycrystalline silicon with an overlying layer of a refractory metal silicide such as MoSi | 03/28/1989 |
| 4797808 | Microcomputer with self-test of macrocode A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. A macrocode word is fetched from an on-chip ROM and stored in an in... | 01/10/1989 |
| 4760555 | Memory array with an array reorganizer A non-volatile memory device formed on a face of a semiconductor substrate which includes an array of electrically programmable read only memory cells, a Y address decoder coupled to said array and first and second sets of input/output lines coupled to sa... | 07/26/1988 |
| 4757504 | Polyphase parity generator circuit A polyphase parity generator circuit for generating parity of multiple bit data values on a data bus during one or more phases of a bus cycle. The circuit includes a prestage circuit having a plurality of parallel decode circuits couplable to respective p... | 07/12/1988 |
| 4757523 | High speed testing of integrated circuit A register of the type used on as address counter in a dynamic RAM is tested by a method which does not require cycling through every possible value of the register contents. The counter is first loaded with a fixed value, all 1's or all 0's, and the cont... | 07/12/1988 |
| 4744858 | Integrated circuit metallization with reduced electromigration The specification discloses a method and a device wherein circuit elements (10) are formed on the surface of a semiconductor body (12). A layer of oxide (22) is applied over the circuit element (10). An aperture (32) is opened through the oxide layer (22)... | 05/17/1988 |
| 4736233 | Interconnect and contact system for metal-gate MOS VLSI devices A simplified process for metal gate and contact/interconnect system for MOS VLSI devices employs a refractory metal structure for the gate, including a thick layer of tungsten alone, with stress and adhesion controlled by the deposition conditions. The me... | 04/05/1988 |
| 4723225 | Programming current controller An electrically programmable semiconductor memory device of a type having an array of programmable semiconductor floating gate transistors sets of which are coupled between associated respective source and drain lines, an array programming control transis... | 02/02/1988 |
| 4721987 | Trench capacitor process for high density dynamic RAM A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar to the N+ bit line, then thick oxide is grow... | 01/26/1988 |
| 4722075 | Equalized biased array for PROMS and EPROMS An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage VBIAS is coupled to each bit line by a ... | 01/26/1988 |
| 4720817 | Fuse selection of predecoder output A fuse selectable decoder for a redundant row of memory elements in an array includes a redundant decode select circuit (38) for receiving predecoder inputs from predecode lines (28), (30), (32) and (34). The predecode lines are output from predecoders (2... | 01/19/1988 |
| 4720819 | Method and apparatus for clearing the memory of a video computer In a video computer system and the like having a bit-mapped RAM component including a shift register, an improved method is provided for rapidly clearing the RAM in order to prepare the system to receive new input data. More particularly, a preselected nu... | 01/19/1988 |
| 4718041 | EEPROM memory having extended life Disclosed is a method and apparatus for extending the programmable life of an EEPROM memory. For each write commamd generated external to the memory an automatic internal read operation is executed. Each internally generated read operation is accompanied ... | 01/05/1988 |
| 4713749 | Microprocessor with repeat instruction A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data memory, with separate address and data paths for program and data. An external program address bus allows off-chip program... | 12/15/1987 |
| 4713748 | Microprocessor with block move instruction A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data memory, with separate address and data paths for program and data. An external program address bus allows off-chip program... | 12/15/1987 |
| 4707626 | Internal time-out circuit for CMOS dynamic RAM A delay circuit for internal clock generation in a dynamic RAM uses a one-shot multivibrator composed of a pair of cross-coupled CMOS NOR gates with a RC delay circuit in the coupling path between the output of one NOR gate and the input of the other. The... | 11/17/1987 |
| 4701633 | Low power clock generator A clock delay circuit of the type used in semiconductor dynamic read/write memory device employs pull-up and pull-down output transistors connected in series between a voltage supply and ground. Excess current in this series path is minimized by a circuit... | 10/20/1987 |
| 4701885 | Dynamic memory array with quasi-folded bit lines A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its in... | 10/20/1987 |
| 4700215 | Polycide electrodes for integrated circuits A semiconductor integrated circuit has electrodes, contacts and interconnects composed of a multilayer structure including a layer of polycrystalline silicon with an overlying layer of a refractory metal silicide such as MoSi2 or WSi2. | 10/13/1987 |
| 4696092 | Method of making field-plate isolated CMOS devices A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positi... | 09/29/1987 |
| 4695979 | Modified four transistor EEPROM cell An electrically erasable programmable memory cell of the four transistor type in which a floating gate transistor has one end of its source to drain path coupled to the write line and the other end to the read line through a read switch. Its control gate ... | 09/22/1987 |
| 4694391 | Compressed control decoder for microprocessor system A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates wi... | 09/15/1987 |
| 4692638 | CMOS/NMOS decoder and high-level driver circuit A decoder and driver circuit for producing an output voltage exceeding the power supply uses a CMOS decode circuit followed by NMOS output stage and pump circuit. The pump clock is derived from a controlled oscillator, and the oscillator is synchronized w... | 09/08/1987 |
| 4692781 | Semiconductor device with electrostatic discharge protection An input protection circuit for an MOS device uses a thick-oxide transistor connected as a diode between a metal bonding pad and ground. The channel width of this transistor is chosen to be sufficient to withstand large, short-duration current spikes caus... | 09/08/1987 |
| 4687951 | Fuse link for varying chip operating parameters Adjustment of operating parameters for a functional circuit is provided by fuse links (44) and (45). For a DRAM, the fuse links (44) control the various internal delays of a timing control generator (40) and fuse links (45) control the sensitivity of sens... | 08/18/1987 |
| 4685089 | High speed, low-power nibble mode circuitry for dynamic memory A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output from the array. Single-bit data-in and data-out terminals for the device are coupled to the 4-bit array input/ou... | 08/04/1987 |
| 4677739 | High density CMOS integrated circuit manufacturing process A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in nitride-framed recesses so a relatively plane surface is prov... | 07/07/1987 |
| 4677586 | Microcomputer device having test mode substituting external RAM for internal RAM A digital data processing system employs a single-chip microcomputer device having separate on-chip program and data memory, executing instructions in a single machine state. An external program address bus allows off-chip program fetch in a memory expans... | 06/30/1987 |
| 4675716 | Insulator coating for improved step coverage in VLSI devices In manufacture of VLSI semiconductor devices, the insulator surface upon which a metallization pattern is deposited is made more smooth by the deposition of a thin insulator in liquid form. This insulator may be silicon oxide deposited from a solution, or... | 06/23/1987 |
| 4672419 | Metal gate, interconnect and contact system for VLSI devices A metal gate and contact/interconnect system for MOS VLSI devices employs a multiple-level refractory metal structure including a thin layer of molybdenum for adhesion to oxide and a thicker layer of tungsten over the molybdenum. The metal gate is encapsu... | 06/09/1987 |
| 4670878 | Column shift circuitry for high speed testing of semiconductor memory devices A semiconductor integrated circuit, such as a high-density, dynamic read/write memory containing an array of rows and columns of memory cells, is constructed to allow high speed testing to identify row line faults in one example, and to identify column or... | 06/02/1987 |
| 4661930 | High speed testing of integrated circuit A register of the type used on as address counter in a dynamic RAM is tested by a method which does not require cycling through every possible value of the register contents. The counter is first loaded with a fixed value, all 1's or all 0's, and the cont... | 04/28/1987 |
| 4661374 | Method of making MOS VLSI semiconductor device with metal gate and clad source/drain Metal-gate transistors with metal silicide cladding of the source/drain regions, as may be used in very high density dynamic RAM devices, are made by a process in which the metal gate is encapsulated in oxide and the cladding is self aligned with the enca... | 04/28/1987 |
| 4658382 | Dynamic memory with improved dummy cell circuitry A semiconductor read/write memory device of the type using dynamic one-transistor storage cells employs dummy capacitors which are the same size as the storage capacitors, and these dummy capacitors are precharged to a reference voltage level less than ha... | 04/14/1987 |
| 4658377 | Dynamic memory array with segmented bit lines A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its in... | 04/14/1987 |
| 4656613 | Semiconductor dynamic memory device with decoded active loads A semiconductor dynamic memory device contains differential sense amplifiers for detecting the charge on bit lines, and active pull-up circuits for restoring bit lines to a full 1 level. The pull-up circuits are not activated on the dummy cell sides, howe... | 04/07/1987 |
