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| Number | Title | Issue Date |
| 4654599 | Four phase clock signal generator A system for and a method of generating a four phase clock signal is disclosed. The system includes an oscillator circuit that generates a clocking signal of frequency F. A flip-flop, under control of a Master Clear signal, establishes the first stage of ... | 03/31/1987 |
| 4633434 | High performance storage unit A large capacity (8 memory banks of 524K error-corrected 36 bit words stored) high performance (latency as low as 240 nanoseconds, 12.8 gigabits/second aggregate data transfer capability with up to 11.4 gigabits/second utilized) pipelined (8 deep request ... | 12/30/1986 |
| 4628217 | Fast scan/set testable latch using two levels of series gating with one current source An economical circuit of n transistors and m resistors (n=4, m=1 for Emitter Coupled Logic (ECL); n=3, m=0 for Current Mode Logic (CML)) interconnects to a fast differential feedback latch of r transistors and s resistors (r=12, s=9 for ECl; r=7, s=3 for ... | 12/09/1986 |
| 4627018 | Priority requestor accelerator A system for accelerating the granting of prioritized memory requests to a multi port memory system of a data processing system is disclosed. The priority requestor accelerator system detects the fact that one remaining requestor is in the priority memory... | 12/02/1986 |
| 4604176 | Method of improving magnetoresistive effect in thin magnetic film A method of fabricating a thin magnetic film having improved magnetoresistive readout characteristics as a binary memory device is disclosed. The film is initially formed from a metal vapor as a series of discrete grains upon a substrate surface that is h... | 08/05/1986 |
| 4600986 | Pipelined split stack with high performance interleaved decode A high performance pipelined virtual first-in first-out stack structure has a data stack portion and a split control stack portion. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input reques... | 07/15/1986 |
| 4595911 | Programmable data reformat system A high speed system utilizing programmably controlled ranks of multiplexers for reformatting data from programmably selected first formats to second formats is described. Interleaved input data is utilized to optimize reformatting rates. The reformatting ... | 06/17/1986 |
| 4594680 | Apparatus for performing quadratic convergence division in a large data processing system A binary division circuit for use in a large data processing system is disclosed which performs division with floating or fixed point numbers. It includes a multiplier unit which is modified to produce the higher precision calculation necessary to the div... | 06/10/1986 |
| 4592005 | Masked arithmetic logic unit An improved masked arithmetic logic unit is disclosed which incorporates at least three principle unique features to optimize implementation in a high speed environment. These features are (1) the inclusion of a mask operand to facilitate mask compares an... | 05/27/1986 |
| 4561006 | Integrated circuit package with integral heating circuit An integrated circuit package having an auxiliary heating element incorporated therein is described. The integral heating element is accessible for application of electric power from an external source to cause heating of the integral circuit package to a... | 12/24/1985 |
| 4556978 | Error checked high speed shift matrix A 72-bit shift matrix, suitable for LSI implementation in gate arrays, is disclosed. Eight byte shifters and eight bit shifters are combined to produce shifts of 0-72 places in either direction, circularly or open ended with zero or sign fill. A means is ... | 12/03/1985 |
| 4549280 | Apparatus for creating a multiplication pipeline of arbitrary size A multiply pipeline with parity circuit to be used as a building block in a multiplication pipeline of arbitrary size is disclosed. It includes circuits for generating and checking parity. The parity of the output carries leaving the component chips of th... | 10/22/1985 |
| 4540228 | Low insertion force connector with improved cam actuator A low insertion force connector for making electrical connection between electrical contacts on a printed circuit board assembly and external circuitry, and having an improved linear cam actuating mechanism is described. An elongated outer housing having ... | 09/10/1985 |
| 4531213 | Memory through checking system with comparison of data word parity before and after ECC processing For use with a digital memory system that generates error correction code signals for storage with associated data words and for correction of detected error(s) in the associated data words when accessed, a system for through checking the accuracy of gene... | 07/23/1985 |
| 4528665 | Gray code counter with error detector in a memory system An improved dynamic memory system including through-checking and error detection of the refresh counter is described. A refresh counter that provides parity of the refresh count for through-checking, of refresh addresses is shown. Error detecting circuitr... | 07/09/1985 |
| 4528640 | Method and a means for checking normalizing operations in a computer device A method and a means are disclosed for the throughchecking of the normalizer operations of an arithmetic unit of a data processing system involving both integer and floating-point formats in single and double precision operations. A post normalizer is use... | 07/09/1985 |
| 4527075 | Clock source with automatic duty cycle correction A clock source for timing and synchronizing the operation of digital data processing equipment and having automatic duty cycle correction is described. A source of signals provides clock signals at a predetermined frequency. A buffer circuit provides the ... | 07/02/1985 |
| 4523314 | Read error occurrence detector for error checking and correcting system An improved error indicating system utilizing adder circuits for use with an error correction code system capable of detecting and indicating multiple bit errors and detecting and correcting single bit errors is described. The system utilizes an encoding ... | 06/11/1985 |
| 4523210 | Fast error checked multibit multiplier A high speed multiplier circuit is disclosed which not only provides increased performance for the multiply operations of a large scale processor but also provides for single bit error detection of results as well. It incorporates a gated carry/save adder... | 06/11/1985 |
| 4520439 | Variable field partial write data merge A variable field partial write system for merging data bits in a memory word or words upon programmable request is described. The variable bit field can be selected for any number of bit positions from a single bit up to and including a full data word, wh... | 05/28/1985 |
| 4517880 | Fan mounting assembly A flexible moulded plastic panel closure is provided with a plurality of latches and retainers to permit the flexible moulded plastic panel to be attached through an aperture in a rigid wall of a chassis of a video display terminal. The flexible moulded p... | 05/21/1985 |
| 4516118 | Pulse width modulation conversion circuit for controlling a color display monitor A video display terminal (VDT) is provided with a controller having six digital logic lines capable of defining sixty-four different colors. An eight color color display monitor (CDM) having three red, green and blue (RGB) video input lines is connected t... | 05/07/1985 |
| 4513290 | Non-resonant coaxial monopole antenna A relatively short broad band monopole coaxial antenna is provided with a center conductor and an outer radiator. The antenna is mounted above a ground plane and comprises a bare outer radiator portion adjacent the ground plane and a portion remote from t... | 04/23/1985 |
| 4513285 | Quasi coherent two-way ranging apparatus An accurate radio frequency ranging system is provided for measuring the time required for a signal to be transmitted from a ground station to a remote station and to be returned to the ground station. The ground station is provided with a master referenc... | 04/23/1985 |
| 4511967 | Simultaneous load and verify of a device control store from a support processor via a scan loop The loading (writing) of plural successive data strings of specifiable bit-length and numbers to a scan/set testable register (called a CONTROL STORE SCAN LOOP STRING) from which it may then be transferred to a control store (called a CONTROL STORE (RAM))... | 04/16/1985 |
| 4509018 | Asymmetric superconducting quantum interference device in a linear amplifier circuit A superconducting quantum interference device (SQUID) is direct current biased through physical connections asymmetric to, and preferably maximally asymmetric to, the two Josephson junctions. The asymmetric SQUID so created is, responsively to such physic... | 04/02/1985 |
| 4506325 | Reflexive utilization of descriptors to reconstitute computer instructions which are Huffman-like encoded A method of and apparatus for encoding computer program instructions and data greatly reduces the total storage requirements. Upon compiling each computer program segment, statistics are generated regarding the frequency of use of each unique program oper... | 03/19/1985 |
| 4504907 | High speed data base search system A high speed data base search system which contains a general purpose computer coupled to a special purpose processor called the High Speed Search Function or HSSF. The HSSF may be external to the computer having a standard Input/Output communication path... | 03/12/1985 |
| 4504827 | Synthetic persistence for raster scan displays A method and apparatus for pseudorandomly decrementing the intensity of data that is displayed on a raster scan display screen. The apparatus essentially comprises means for selecting and partially decrementing data from an image memory and means for cont... | 03/12/1985 |
| 4504782 | Detection of catastrophic failure of dielectric, improper connection, and temperature of a printed circuit assembly via one wire A first sensor for the detection of dielectric failure (by burning) within a multilayer printed circuit assembly comprises an isolated conductive layer. This first sensor is connected by a first diode to a single wire which also connects a second, tempera... | 03/12/1985 |
| 4504156 | Cooling system monitor assembly and method A cooling system monitoring assembly incorporating a heat generating element for simulating heat generation of components in the system, together with heat sensing element responsive to the heat generating element for providing temperature signals when th... | 03/12/1985 |
| 4502823 | Broken drill bit detector A Drill Bit detector for use with numerically controlled drilling machine capable of sensing missing or broken Drill Bits in the range of 1 mil to 30 mils in diameter, or larger, is described. An infrared emitting diode is driven at a predetermined freque... | 03/05/1985 |
| 4500988 | VLSI Wired-OR driver/receiver circuit Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supporte... | 02/19/1985 |
| 4498177 | M Out of N code checker circuit An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators... | 02/05/1985 |
| 4498058 | Low input capacitance amplifier A first feedback loop to a regulator transistor within the drain circuit of the input field effect transistor (FET) serves to maintain the voltage across the drain-gate junction of the input FET at a constant value consistent with FET operation as a sourc... | 02/05/1985 |
| 4494064 | Direct current inrush limiting circuit Direct current inrush upon connection of a capacitive load to a d.c. voltage is limited through an intermediary circuit. Within such circuit the inrush current is sensed by a series resistance and such sensing is utilized via a feedback loop, to control a... | 01/15/1985 |
| 4486848 | Microprocessor parallel additive execution of a computer count ones instruction A data word of less than or equal to 2N bits is counted for the number of binary "1's" contained therein in log2 2N =N cycles of 3 steps each in a microprocessor. As a first step the data in a first register is logically A... | 12/04/1984 |
| 4484301 | Array multiplier operating in one's complement format A method and apparatus for performing a two's complement, single or double precision digital multiply, whereby the multiplication is performed in a one's complement format in a gate array assembly and then converted to a two's complement format. The gate ... | 11/20/1984 |
| 4484276 | Shift matrix preselector control circuit A computer digital logic circuit utilizing an encoded Read Only Memory (ROM) and multiplexor elements is used to translate top-level shift control signals, such as arise from instruction translation, into the low-level control of selecting data input to, ... | 11/20/1984 |
| 4484270 | Centralized hardware control of multisystem access to shared and non-shared subsystems A centralized control unit for use in a multisystem data processing configuration to provide dynamic access to shared and non-shared peripheral subsystems is disclosed. This unit, known herein as a subsystem access unit (SAU) is able to remotely control o... | 11/20/1984 |
