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| Number | Title | Issue Date |
| 7752586 | Design structure of an integration circuit and test method of the integrated circuit A design structure for an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates by using a first clock signal CLK 1; a second flip-flop DFF 2 which operates by using a second clock signal CLK 2, and... | 07/06/2010 |
| 7441006 | Reducing number of write operations relative to delivery of out-of-order RDMA send messages by managing reference counter An RNIC implementation that performs direct data placement to memory where all segments of a particular connection are aligned, or moves data through reassembly buffers where all segments of a particular connection are non-aligned. The type of connection that cuts-t... | 10/21/2008 |
| 7393419 | Conductive adhesive rework method A method of removing cured conductive polymer adhesives, disclosed here as thermal interface materials, from electronic components for reclamation or recovery of usable parts of module assemblies, particularly high cost semiconductor devices, heat sinks and other mo... | 07/01/2008 |
| 7386732 | Integrated system security method Logic scan based design and electronic fuse (e-fuse) technology are combined to create a circuit macro function that is integrated in a non-critical area of a processor chip or related circuit to provide a new means of securing electronic systems and devices such as... | 06/10/2008 |
| 7386358 | Available to promise allocation optimization tool A distributed, network-based system, method, and computer program product determines an optimal allocation of available to promise components in a supply chain. An aggregate demand request is generated by a demand entity intelligent agent. The aggregate demand reque... | 06/10/2008 |
| 7358586 | Silicon-on-insulator wafer having reentrant shape dielectric trenches A bonded SOI wafer and a method for forming a bonded SOI wafer are provided. According to the disclosed method, a first semiconductor wafer is provided, having a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric fil... | 04/15/2008 |
| 7356147 | Method, system and program product for attaching a title key to encrypted content for synchronized transmission to a recipient A method and system for attaching a title key to encrypted content for synchronized transmission to, or storage by, a recipient is provided. Specifically, under the present invention, an elementary media stream is parceled into content units that each include a cont... | 04/08/2008 |
| 7348252 | Method of forming silicon-on-insulator wafer having reentrant shape dielectric trenches A method for forming a bonded SOI wafer is provided in which a first wafer having a single-crystal semiconductor region has a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the oute... | 03/25/2008 |
| 7345904 | Method for programming an electronically programmable semiconductor fuse A method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. The fuse link has a nominal maximum programming current and corresponding combinations of a programming voltage an... | 03/18/2008 |
| 7346094 | System and method for transmitting data and additional information simultaneously within a wire based communication system A system and method is provided for transmitting data signals and additional information signals having partially overlapping frequency bands simultaneously within a wire based communication system over the same wired medium using a spread spectrum technique for mod... | 03/18/2008 |
| 7340496 | System and method for determining the Nth state of linear feedback shift registers The Nth state of an n-stage linear feedback shift register (LFSR) used to generate pseudo random binary sequences or patterns, and which may be configured as a multiple input signature register (MISR) or single input signature register (SISR) to compress data and ge... | 03/04/2008 |
| 7328244 | Electronic mail system The present invention discloses a method and apparatus, preferably embodied as a computer program product, wherein e-mail is classified according to categories by imbedding a category identifier into the header of the e-mail message. The invention also provides for ... | 02/05/2008 |
| 7312261 | Thermal interface adhesive and rework A reworkable conductive adhesive composition, and method of making such, comprising an epoxy based conductive adhesive containing conductive metal filler particles dispersed in a solvent-free hybrid epoxy polymer matrix. In an additional embodiment an improved metho... | 12/25/2007 |
| 7302757 | Micro-bumps to enhance LGA interconnections An improved Land Grid Array interconnect structure is provided with the use of small metal bumps on the substrate electrical contact pad. The bumps interlock with segments of the fuzz button connection and increase the physical contact surface area between the conta... | 12/04/2007 |
| 7302307 | Micrologistics tracking system and method for an automated manufacturing facility A method of monitoring activity in an automated fabrication facility in which work-in-process material lots undergo manufacturing operations and storage operations includes tracking processing load and unload times of the lots at each of the manufacturing operations... | 11/27/2007 |
| 7247363 | Supported greensheet structure and method in MLC processing Methods for forming and the intermediate greensheet products formed are provided by attaching a removable support film to a first surface of a greensheet and a frame to a second surface of the greensheet. The support film is preferably a peelable support film cast t... | 07/24/2007 |
| 7241668 | Planar magnetic tunnel junction substrate having recessed alignment marks A method for forming an alignment mark structure for a semiconductor device includes forming an alignment recess at a selected level of the semiconductor device substrate. A first metal layer is formed over the selected substrate level and within the alignment reces... | 07/10/2007 |
| 7202187 | Method of forming sidewall spacer using dual-frequency plasma enhanced CVD A silicon nitride spacer material for use in forming a PFET device and a method for making the spacer includes the use of a dual-frequency plasma enhanced CVD process wherein the temperature is in the range depositing a silicon nitride layer by means of a low-temper... | 04/10/2007 |
