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| Number | Title | Issue Date |
| 6877089 | Branch prediction apparatus and process for restoring replaced branch history for use in future branch predictions for an executing program Apparatus and methods implemented in a processor semiconductor logic chip for providing novel “hint instructions” that uniquely preserve and reuse branch predictions replaced in a branch history table (BHT). A branch prediction is lost in the BHT after its assoc... | 04/05/2005 |
| 6721335 | Segment-controlled process in a link switch connected between nodes in a multiple node network for maintaining burst characteristics of segments of messages Defines and handles segments in messages to place pauses and interruptions within the communication of a message between transmitted segments of the message. A common link switch is used in a network to connect links to all nodes, the segment structures in each mess... | 04/13/2004 |
| 5894583 | Variable timeout method for improving missing-interrupt-handler operations in an environment having I/O devices shared by one or more systems Missing interrupt handler (MIH) software features for supporting a variable MIH timeout for I/O requests issued by an operating system (OS). The MIH timeout is varied to prevent a false indication of a failure in an I/O device operation, which is indicate... | 04/13/1999 |
| 5842881 | Substrate-embedded pluggable receptacles for connecting clustered electrical cables to a module A pluggable connector capable of connecting a large number of electrical transmission lines per connector, and small enough to enable a large number of connectors to be added to a multi-chip module. For example, 5 or 6 of these connectors can add over a h... | 12/01/1998 |
| 5768620 | Variable timeout method in a missing-interrupt-handler for I/O requests issued by the same operating system Missing interrupt handler (MIH) internal software features support a variable MIH timeout for I/O requests issued by an operating system (OS), when the same OS is involved with both an executing I/O request and a waiting I/O request. The OS varies its MIH... | 06/16/1998 |
| 5761488 | Logic translation method for increasing simulation emulation efficiency A method of speeding up computer simulation/emulation of circuit logic designs. The method converts an original circuit logic design (intended for hardware packaging) to a different circuit form before starting computer simulation/emulation. The converted... | 06/02/1998 |
| 5758190 | Control unit threshold timeout controls for software missing interrupt handlers in operating systems I/O control unit (CU) features for supporting multiple host operating systems (OSs) which use missing interrupt handler (MIH) timeout functions for detecting potential failures of requested I/O device operations. These CU features support multiple host OS... | 05/26/1998 |
| 5671441 | Method and apparatus for automatic generation of I/O configuration descriptions Automatic machine methods and apparatus for determining which components of an I/O configuration are shared by other components of the configuration. The information can be obtained through the use of existing self-description facilities and unique identi... | 09/23/1997 |
| 5664219 | Method and system for controlling servicability of adapters connected by an I/O channel interface to a computer system A method and system to eliminate service hardware previously provided with an adapter by providing a novel way to transfer its hardware service functions to a remote service hardware found elsewhere in a computer system, such as a mainframe. The transferr... | 09/02/1997 |
| 5655146 | Coexecution processor isolation using an isolation process or having authority controls for accessing system main storage A coexecutor for executing functions offloaded from central processors (CPs) in a data processing system, as requested by one or more executing control programs, which include a host operating system (host OS), and subsystem programs and applications exec... | 08/05/1997 |
| 5652914 | Method and system for superimposing, creating and altering I/O applications and controls within an I/O subsystem by using an I/O subchannel intercept field An Internal I/O Facility (iIOF) having a general interface for executing I/O related applications in an Input/Ouput SubSystem (IOSS) of a computer system. IIOF applications are executed in the IOSS outside the scope of CPU applications executed under the ... | 07/29/1997 |
| 5646676 | Scalable interactive multimedia server system for providing on demand data Connects a host computer system (such as a mainframe or host server system) to a large multimedia (MM) distribution network having wide scalability without being limited by bandwidth constraints in the host system or in any multimedia controller for contr... | 07/08/1997 |
| 5611696 | High density and high current capacity pad-to-pad connector comprising of spring connector elements (SCE) A new approach to providing thousands of contacts between electronic packages and their next package level by use of small formed spring contact elements (SCE) retained within a interposer structure or soldered directly into a printed circuit board or ont... | 03/18/1997 |
| 5613086 | Method and system for locking a page of real storage using a virtual address A LOCK PAGE instruction is provided for locking a page of real storage using a virtual address. The LOCK PAGE instruction includes an operation code which specifies the operation to be performed, a first operand which contains the value of the real addres... | 03/18/1997 |
| 5610603 | Sort order preservation method used with a static compression dictionary having consecutively numbered children of a parent A method of performing Ziv-Lempel type data compression while preserving in the compressed records any sort ordering of the uncompressed records. The method assigns the necessary ordered numbering to the code words for character strings in a static compre... | 03/11/1997 |
| 5608966 | Process for manufacture of spring contact elements and assembly thereof A method of manufacturing thousands of contacts between electronic packages and their next package level by use of small wires retained within a interposer structure or soldered directly into a printed circuit board or onto the module. Each wire can be ei... | 03/11/1997 |
| 5604863 | Method for coordinating executing programs in a data processing system A method for coordinating phases of program execution within a data processing system. One or more program defined synchronization events are established. Each synchronization event is responded to by one or more programs to coordinate phases of execution... | 02/18/1997 |
| 5600805 | Pass-through for I/O channel subsystem call instructions for accessing shared resources in a computer system having a plurality of operating systems Enables any OS of plural OSs within any of plural logical-resource partitions (LPARs) of a CEC to use interpretive execution for synchronously-executable CHSC (channel subsystem call) commands. A CHSC command authorization mask (CCAM) is provided to contr... | 02/04/1997 |
| 5577231 | Storage access authorization controls in a computer system using dynamic translation of large addresses A method of using the DAT mechanism in a computer processor to extend both: 1) the native storage access authorization architecture of the processor, and 2) to enable the processor to execute programs designed to operate under different storage access arc... | 11/19/1996 |
| 5560013 | Method of using a target processor to execute programs of a source architecture that uses multiple address spaces A method of utilizing large virtual addressing in a target computer to implement an instruction set translator (1ST) for dynamically translating the machine language instructions of an alien source computer into a set of functionally equivalent target com... | 09/24/1996 |
| 5551013 | Multiprocessor for hardware emulation A software-driven multiprocessor emulation system comprising a plurality of emulation processors connected in parallel in a module. One or more modules of processors comprise an emulation system. An execution unit in each processor includes a table-lookup... | 08/27/1996 |
| 5548507 | Language identification process using coded language words Provides a process which identifies the language or genre of a stored or transmitted document. The process uses a plurality of Word Frequency Tables (WFTs) respectively associated with languages/genre of interest. Each WFT contains a relatively few of the... | 08/20/1996 |
| 5544345 | Coherence controls for store-multiple shared data coordinated by cache directory entries in a shared electronic storage A high-speed cache is shared by a plurality of independently-operating data systems in a multi-system data sharing complex. Each data system has access both to the high-speed cache and to lower-speed, upper-level storage for obtaining and storing data. Ma... | 08/06/1996 |
| 5537574 | Sysplex shared data coherency method A method for controlling coherence of data elements sharable among a plurality of independently-operating CPCs (central processing complexes) in a multi-system complex (called a parallel sysplex) which contains sysplex DASDds (direct access storage device... | 07/16/1996 |
| 5537606 | Scalar pipeline replication for parallel vector element processing A central processor (which may be entirely contained in a single semiconductor chip), that performs vector operations using scalar machine resources. The processor incorporates multiple parallel scalar execution unit pipelines, which do not contain hardwa... | 07/16/1996 |
| 5530663 | Floating point unit for calculating a compound instruction A+B×C in two cycles A floating point arithmetic unit that executes a single compound instruction that produces the result A+B×C with A, B and C being floating point numbers. Arithmetic on the exponents of A, B and C provide a normalized result of the multiplication before t... | 06/25/1996 |
| 5524132 | Process for revealing defects in testpieces using attenuated high-energy x-rays to form images in reusable photographs A process and apparatus for revealing manufacturing defects in testpieces, such as printed circuit boards, by passing through high-intensity attenuated x-rays (above 150 Kilo-Volts) to reusable photo plates for revealing defects in the testpieces. The x-r... | 06/04/1996 |
| 5508732 | Data server, control server and gateway architecture system and method for broadcasting digital video on demand A data processing system is described for providing digital video information on subscriber demand, for very large video data files. The system enables rapid response to the requests by network subscribers, independent of the number of video files offered... | 04/16/1996 |
| 5495614 | Interface control process between using programs and shared hardware facilities A control process which enables a non-supervisory "using program" (e.g. application programs) to directly interface one or more shared asynchronous hardware facilities in a computer system. Any using program may request the operating system (OS) to set up... | 02/27/1996 |
| 5493661 | Method and system for providing a program call to a dispatchable unit's base space A method and system for providing a PROGRAM CALL to a dispatchable unit's base space is described herein. A program call to a dispatchable unit's (PC to DU) base space bit is added to each entry-table entry in order to determine whether a PROGRAM CALL to ... | 02/20/1996 |
| 5493668 | Multiple processor system having software for selecting shared cache entries of an associated castout class for transfer to a DASD with one I/O operation A high-speed cache is shared by a plurality of independently-operating data systems in a multi-system data sharing complex. Each data system has access both to the high-speed cache and the lower-speed, secondary storage for obtaining and storing data. Man... | 02/20/1996 |
| 5490261 | Interlock for controlling processor ownership of pipelined data for a store in cache Insures data integrity in process ownership indications by providing an ownership interlock on the data units in a pipeline to a store-in type of cache. An ownership interlock prevents any processor ownership change to occur (i.e. exclusive or readonly ow... | 02/06/1996 |
| 5463754 | Shared direct access storage device for fixed block architecture devices A shared fixed block architecture direct access storage system and method for use with a plurality of computer systems is described. The storage system includes a shared fixed block architecture direct access storage device with a plurality of shared file... | 10/31/1995 |
| 5461721 | System for transferring data between I/O devices and main or expanded storage under dynamic control of independent indirect address words (IDAWs) Enables an I/O channel program to use IDAWs (indirect data address words) to control data transfers from/to an I/O (input/output) device to/from either or both of ES (expanded storage) and/or system MS (main storage), in which data moved to/from ES does n... | 10/24/1995 |
| 5459864 | Load balancing, error recovery, and reconfiguration control in a data movement subsystem with cooperating plural queue processors Provides load balancing, recovery and reconfiguration control for a data move subsystem comprised of a plurality of interconnected and cooperating data move processors (DMPs). Each DMP processor has an associated queue for receiving queue elements (QEs) f... | 10/17/1995 |
| 5457793 | Software cache management of a shared electronic store in a supplex Storage is managed in a shared electronic store (SES) by assigning storage classes (STCs) to each directory entry having a data item stored in SES. The assignments of directory entries and data elements to the respective STCs can be changed at any time by... | 10/10/1995 |
| 5454086 | Dynamic program analyzer facility Provides a dynamic execution link between an analyzer program and each hook instruction in a program. Special types of hook instructions are provided for use in a hooked program. The link causes the analyzer program to execute as part of a continuous unin... | 09/26/1995 |
| 5452455 | Asynchronous command support for shared channels for a computer complex having multiple operating systems This invention involves reconfiguration support for shared I/O resources in a a computer electronic complex (CEC) supporting both shared and unshared I/O channels of the type described and claimed in U.S. patent application Ser. No. 07/898,867 (PO9-92-016... | 09/19/1995 |
| 5450508 | Apparatus and method for optical fiber alignment using adaptive feedback control loop A servo-feedback method with elements for dynamically aligning a pair of mating ends of optical fibers supported in a pluggable connector. At least one of the mating ends in the pair receives light from the other mating end. The light-receiving end is mec... | 09/12/1995 |
| 5450590 | Authorization method for conditional command execution One or more central processing complexes (CPC's), each with one or more programs being executed, issue commands to a structured electronic storage (SES). The commands include ones that create or delete data structures in SES, and attach or detach users to... | 09/12/1995 |
