Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7199306 | Multi-strand substrate for ball-grid array assemblies and method A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M... | 04/03/2007 |
| 7074687 | Method for forming an ESD protection device An ESD protection device (20) comprises an N-type epitaxial collector (21), a first, lightly doped, deep base region (221) and second, highly doped, shallow base region (222) that extends a predetermined lateral dimension. The device resp... | 07/11/2006 |
| 6986971 | Reflective mask useful for transferring a pattern using extreme ultraviolet (EUV) radiation and method of making the same An EUV mask (10) includes an opening (26) that helps to attenuate and phase shift extreme ultraviolet radiation using a subtractive rather than additive method. An etch stop layer (20) may be provided between a lower multilayer reflective stack ... | 01/17/2006 |
| 6963090 | Enhancement mode metal-oxide-semiconductor field effect transistor An implant-free enhancement mode metal-oxide semiconductor field effect transistor (EMOSFET) is provided. The EMOSFET has a III-V compound semiconductor substrate and an epitaxial layer structure overlying the III-V compound semiconductor substrate. The epitaxial ma... | 11/08/2005 |
| 6936763 | Magnetic shielding for electronic circuits which include magnetic materials Shielded electronic integrated circuit apparatus (5) includes a substrate (10), with an eletronic integrated circuit (15) formed thereon, and a dielectric region (12) positioned on the electronic integrated circuit. The dielectric region ... | 08/30/2005 |
| 6894353 | Capped dual metal gate transistors for CMOS process and method for making the same A first gate (120) and a second gate (122) are preferably PMOS and NMOS transistors, respectively, formed in an n-type well (104) and a p-type well (106). In a preferred embodiment first gate (120) includes a first metal layer (... | 05/17/2005 |
| 6828618 | Split-gate thin-film storage NVM cell A semiconductor nonvolatile memory cell (30) comprising a split-gate FET device having a charge-storage transistor (38) in series with a select transistor (39). A multilayered charge-storage gate dielectric (35) extends over at least a po... | 12/07/2004 |
| 6801322 | Method and apparatus for IN SITU measuring a required feature of a layer during a polishing process The invention relates to a method for measuring a required feature of a thin layer (4) used in a polishing process that is carried out by a polish head by producing a localized temperature rise on the surface of the layer (4) by focusing a short pump l... | 10/05/2004 |
| 6787421 | Method for forming a dual gate oxide device using a metal oxide and resulting device A semiconductor device (10) having two different gate dielectric thicknesses is formed using a single high-k dielectric layer, preferably a metal oxide. A thicker first gate dielectric (16) is formed in a region of the device for higher voltage require... | 09/07/2004 |
| 6770923 | High K dielectric film A dielectric layer comprises lanthanum, aluminum, nitrogen, and oxygen and is formed between two conductors or a conductor and substrate. In one embodiment, the dielectric layer is graded with among the lanthanum, nitrogen, or aluminum. An additional insulating laye... | 08/03/2004 |
| 6744117 | High frequency semiconductor device and method of manufacture A semiconductor device (10) having a gate (15), a source (19), and a drain (20) with a gate bus (25) and first ground shield (24) patterned from a first metal layer and a second ground shield (31) patterned from a sec... | 06/01/2004 |
| 6710265 | Multi-strand substrate for ball-grid array assemblies and method A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M... | 03/23/2004 |
| 6709312 | Method and apparatus for monitoring a polishing condition of a surface of a wafer in a polishing process A method for monitoring a polishing condition of a surface of a wafer in a polishing process is provided, the method comprising providing a wafer (16) to be polished, the wafer (16) having at least one optically distinguishable feature (20) belo... | 03/23/2004 |
| 6634385 | Apparatus for conveying fluids and base plate The invention relates to an apparatus for conveying at least one fluid, comprising at least a first fluidic element (10) and a second fluidic element (30) connected to each other for conveying said fluid, and a base plate (24) to which said first fluidic ... | 10/21/2003 |
| 6465743 | Multi-strand substrate for ball-grid array assemblies and method A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board (11) having a plurality of BGA substrates (12) arranged in N rows (14) and M columns (16) to form an N by M array. N and M are greater than... | 10/15/2002 |
| 6461898 | Two step wire bond process A two step wire bonding process is used to ultrasonically attach a wire (18) to a contact pad (13) on a semiconductor device (10). A first step is used to flatten a rounded tip (19) of the wire (18), and to start the bonding process. This is accomplished ... | 10/08/2002 |
| 6307904 | Clock recovery circuit An edge detector (10) detects edges of clock pulses in a digital signal and provides edge detect pulses to a state corrector (20). A state sequencer (15) receives a clock signal and steps through a sequence of states in accordance with the clock signal to... | 10/23/2001 |
| 6305708 | Air bag deployment system and method for monitoring same An air bag deployment system (20) includes a microcontroller (21), an inflator (23), and an inflator sensor (24). The inflator sensor (24) is adjacent to the inflator (23) and monitors the firing of the inflator (23). The inflator sensor (24) monitors the... | 10/23/2001 |
| 6302775 | Apparatus and method for cold cross-sectioning of soft materials Apparatus and a method of cold cross-sectioning soft materials includes providing a chuck attached to a drive motor with a composite plate attached to the chuck and including a heat insulating portion, a heat conducting layer, and a central axially extend... | 10/16/2001 |
| 6303978 | Optical semiconductor component and method of manufacture An optical semiconductor component includes a semiconductor substrate (120) and a packaging material (140) located over the semiconductor substrate. The packaging material includes an optically transparent cycloaliphatic polymer (142, 242, 400, 600). A me... | 10/16/2001 |
| 6144611 | Method for clearing memory contents and memory array capable of performing the same The present invention provides a means for clearing or wiping the contents of a RAM array without the need for overly large transistors and without experiencing current spikes by using a progressive row-by-row clearing operation. In reference to FIGS. 4 a... | 11/07/2000 |
| 6027997 | Method for chemical mechanical polishing a semiconductor device using slurry Conductive plugs (28) are formed in a semiconductor device (10) using a chemical mechanical polishing (CMP) process. A blanket conductive layer (26), for example of tungsten, is deposited in a plug opening (24). The conductive layer is polished back by CM... | 02/22/2000 |
| 5966635 | Method for reducing particles on a substrate using chuck cleaning Particles counts and concentrations are reduced from the backside of a substrate, such as a semiconductor wafer or flat panel display with the invention, to improve precision and uniformity in subsequent operations, including lithography operations. A sem... | 10/12/1999 |
| 5702981 | Method for forming a via in a semiconductor device A method for forming vias in a semiconductor device improves the resistance and reliability of contacts formed by use of an etch stop layer during the via formation process. An etch stop layer (40), preferably a silicon nitride or aluminum nitride layer, ... | 12/30/1997 |
| 5691242 | Method for making an electronic component having an organic substrate A method for packaging an integrated circuit begins by providing an organic substrate (310) having at least one device site (312). Within each device site, one or more electronic devices (532) is mounted. Around the device site, slots (316) and corner hol... | 11/25/1997 |
| 5677231 | Method for providing trench isolation A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric ... | 10/14/1997 |
| 5665281 | Method for molding using venting pin A molding method is used to mold a semiconductor device within a molded carrier ring. A mold tool (30) has an upper platen (32) and a lower platen (34). Each platen has a package cavity (36) and a carrier ring cavity (38). Between the package and ring cav... | 09/09/1997 |
| 5652176 | Method for providing trench isolation and borderless contact A trench isolation region (32) is fabricated to include a trench liner (28) comprised of aluminum nitride. The aluminum nitride trench liner is useful in borderless contact applications wherein a contact opening (56) is etched in an interlayer dielectric ... | 07/29/1997 |
| 5646060 | Method for making an EEPROM cell with isolation transistor An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source reg... | 07/08/1997 |
| 5639989 | Shielded electronic component assembly and method for making the same Electronic components are shielded from electromagnetic interference (EMI) by one or more conformal layers filled with selected filler particulars for attenuate specific EMI frequencies or a general range of frequencies. Shielding is accomplished through ... | 06/17/1997 |
| 5633186 | Process for fabricating a non-volatile memory cell in a semiconductor device A process for fabricating a non-volatile memory cell (10) in a semiconductor device includes the formation of a doped region (28) in a semiconductor substrate (40) underlying a floating gate electrode (16) and separated therefrom by a tunnel dielectric la... | 05/27/1997 |
| 5605865 | Method for forming self-aligned silicide in a semiconductor device using vapor phase reaction Self-aligned silicide regions (24) are formed in a semiconductor device (10) using vapor phase reaction. A chemical vapor deposition system (40) is used, but rather than depositing a blanket silicide material, a precursor (48) is introduced into the react... | 02/25/1997 |
| 5583376 | High performance semiconductor device with resin substrate and method for making the same High performance semiconductor devices, such as those used to package microprocessor integrated circuits, demand materials with excellent electrical, physical and chemical properties. Polymethylpentene (PMP) compositions provide resin substrates for high ... | 12/10/1996 |
| 5583377 | Pad array semiconductor device having a heat sink with die receiving cavity A semiconductor device (10) provides heat dissipation while maintaining a low profile. The device includes a circuitized substrate (12) having an opening (20). Inserted into, or at least covering, the opening is a heat sink (22) having a base portion (24)... | 12/10/1996 |
| 5578523 | Method for forming inlaid interconnects in a semiconductor device In the present invention, an inlaid interconnect (44) is formed by chemical mechanical polishing. A polish assisting layer (31), in the form of an aluminum nitride layer, is formed between an interlayer dielectric (30) and an interconnect metal (42) to pr... | 11/26/1996 |
| 5566877 | Method for inspecting a semiconductor device A method for inspecting a semiconductor device includes an inspection station (10), a handling system (12), a microscope (14), a camera (18), and a computer (20) having a monitor (22). A magnified image (40) of the device being inspected is transmitted to... | 10/22/1996 |
| 5559054 | Method for ball bumping a semiconductor device A ball bump is formed on a semiconductor die (12) by lowering a capillary (18) and a conductive wire (20) having a ball (30) formed at its end toward the die. The ball is pressed against a bond pad (14) of the die to form a ball bond (32). The capillary i... | 09/24/1996 |
| 5554940 | Bumped semiconductor device and method for probing the same Probing array bumped semiconductor devices using cantilever probe needles is facilitated by the formation of peripheral test pads. A semiconductor die (10) includes bond pads (12). A redistribution metallization layer is deposited and patterned to form in... | 09/10/1996 |
| 5554870 | Integrated circuit having both vertical and horizontal devices and process for making the same An integrated circuit (10) has a vertical device, such as a transistor (71), formed by epitaxial growth from a substrate (12) and a horizontal device, such as a transistor (73, 75) grown epitaxially from the vertical device. In accordance with one embodim... | 09/10/1996 |
| 5536677 | Method of forming conductive bumps on a semiconductor device using a double mask structure A method for forming conductive bumps (60, 62) on a semiconductor device (50) using a mask structure (20) employs two masks (22, 24) individually fabricated and positioned in a back-to-back relationship. Each mask is patterned and isotropically etched to ... | 07/16/1996 |
