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Attorney: Glick; K. R.


Number of patents: 16
Last date: March 10, 1992

NumberTitleIssue Date
5095343Power MOSFET
A VDMOS device includes a wafer of semiconductor material having first and second opposed major surfaces. A drain region of a first conductivity type extends along the one major surface. A plurality of body regions of a second conductivity type is in the ...
03/10/1992
5053345Method of edge doping SOI islands
SOI islands having doped edges are formed by providing over the surface of a layer of single crystalline silicon on an insulating substrate a masking layer formed of two layers, the lowermost layer adjacent the silicon layer being silicon oxide and the up...
10/01/1991
5049973Heat sink and multi mount pad lead frame package and method for electrically isolating semiconductor die(s)
A packaging assembly for electrical components includes a heat sink having a mounting surface upon which certain ones of the electrical components are mounted. An associated lead frame is rigidly secured to an edge of the heat sink, and one or more extend...
09/17/1991
5038197Hermetically sealed die package with floating source
An hermetically sealed package for a die comprised of a base plate, a side wall mounted on the brace plate, a printed circuit board connecting terminals on one side of the die to a first lead, connector clips connecting terminals on the other side of die ...
08/06/1991
5023692Power MOSFET transistor circuit
The present invention relates to a power MOS transistor having a current limiting circuit incorporated in the same substrate as the transistor. The power MOS transistor includes a drain region extending through the substrate between opposed first and seco...
06/11/1991
4964726Apparatus and method for optical dimension measurement using interference of scattered electromagnetic energy
A dimension of an object disposed on a substrate, such as the width of a line of material deposited on a substrate in an integrated circuit manufacturing procedure, is measured by directing a plane wave of electromagnetic energy of predetermined dimension...
10/23/1990
4945070Method of making cmos with shallow source and drain junctions
A CMOS device having shallow source and drain regions is formed in a body of single crystalline silicon having a major surface by forming in the body adjacent well regions of opposite conductivity type having an isolation region of an insulating material ...
07/31/1990
4933994Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide
A method for using a self-aligned metallic mask for formation of a shallow source/drain, lightly doped drain metal-oxide-semiconductor device having a self-aligned low-resistivity silicide/polysilicon gate for greater device speed. The invention involves ...
06/19/1990
4927777Method of making a MOS transistor
A method of making a MOS transistor having source and drain extensions includes forming on a surface of a substrate of single crystalline silicon a gate line having a thin layer of silicon oxide between the gate line and the substrate surface. A light dos...
05/22/1990
4923826Method for forming dielectrically isolated transistor
A method for forming dielectrically isolated devices comprises forming a first insulating layer on a flat monocrystalline surface of a silicon wafer. A plurality of active regions is defined on the surface using existing manufacturing masks. Portions of t...
05/08/1990
4901135Hermetically sealed housing with welding seal
A hermetically sealed housing for a solid state device or the like includes a metal header having a mounting surface and a metal cap mounted on the header and over the mounting surface. The cap includes a cup-shaped portion and a flange extending radially...
02/13/1990
4897366Method of making silicon-on-insulator islands
A silicon-on-insulator (SOI) semiconductor device is made by forming a layer of single crystalline silicon on the surface of an insulating substrate. Portions of the silicon layer are removed, such as by etching, to form islands of the single crystalline ...
01/30/1990
4809045Insulated gate device
An insulated gate device includes at least one cell having base and emitter region surfaces disposed in ohmic contact with a metallic emitter electrode. The cell is constructed to provide a larger ratio of base region surface area to emitter region surfac...
02/28/1989
4803533IGT and MOSFET devices having reduced channel width
During fabrication of an insulated gate device, a drain-forming dopant having a relatively low diffusion coefficient is implanted along a substrate surface which overlaps the boundary between a to-be-formed vertical drain region and a to-be-formed adjacen...
02/07/1989
4700460Method for fabricating bidirectional vertical power MOS device
A vertical MOSFET in a silicon wafer having opposing major surfaces includes a source electrode on one surface, a drain electrode on the second surface, and an internally disposed insulated gate. The silicon between the insulated gate and each of the majo...
10/20/1987
4237600Method for fabricating stacked semiconductor diodes for high power/low loss applications
A semiconductor wafer is appropriately doped to create a P-N or P-I-N junction, and metallized on both its planar surfaces with electrode material. The wafer is then bonded to a second similarly processed wafer. Without damaging the semiconductor material...
12/09/1980
 
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