Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 8174969 | Congestion management for a packet switch A packet switch includes a flow control circuit for preventing a downstream ingress port of the packet switch from providing a non-posted packet to an upstream egress port of the packet switch when a downstream egress port of the packet switch is congested. As a res... | 05/08/2012 |
| 8164367 | Spread spectrum clock generation technique for imaging applications A clock signal generator includes a phase-lock loop for generating an imaging clock signal having a frequency based on a reference clock signal. The imaging clock signal generator also includes a modulation circuit for determining a number of pixels in a horizontal ... | 04/24/2012 |
| 8161210 | Multi-queue system and method for deskewing symbols in data streams A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a deskew unit for each data stream, each of which inclu... | 04/17/2012 |
| 8149224 | Computing system with detachable touch screen device A computing system includes a computer device and a detachable touch screen device. The computer device receives input from a touch screen of a detachable touch screen device when the detachable touch screen device is attached to a touch screen port of the computer ... | 04/03/2012 |
| 8081646 | Old virtual queues technique for routing data packets in a packet switch A packet switch includes virtual output queues for mapping data units of data packets from input ports to output ports of the packet switch. The packet switch selects virtual output queues based on old age indicators of the virtual output queues and routes data unit... | 12/20/2011 |
| 8069392 | Error correction code system and method An error correction code system includes an error correction code generator for generating an error correction code based on a data unit and an error detector for detecting at least one bit error in the data unit based on the error correction code. The error correct... | 11/29/2011 |
| 8040888 | Packet switch with port route tables A packet switch includes individual route tables for ports of the packet switch. Each route table is associated with a port and individually maps a destination identifier of a data packet received at the port to another port in the packet switch. In some embodiments... | 10/18/2011 |
| 8028211 | Look-ahead built-in self tests with temperature elevation of functional elements A method and apparatus are disclosed for predicting the failure of a functional element of an integrated circuit during operation. The method includes determining whether the functional element of the integrated circuit device is in an idle cycle, elevating the temp... | 09/27/2011 |
| 8018289 | Holdover circuit for phase-lock loop A clock circuit includes a phase-lock loop and a holdover circuit. The phase-lock loop generates an output clock signal having a constant frequency based on a loop filter voltage of a loop filter in the phase-lock loop. The holdover circuit generates and stores a di... | 09/13/2011 |
| 8014288 | Packet latency based arbitration technique for a packet switch A packet switch including input ports having various input bandwidths initializes credit values for the input ports. An arbiter of the packet switch selects input ports based on the credit values and routes data packets from the selected input ports to a switch fabr... | 09/06/2011 |
| 7995696 | System and method for deskewing data transmitted through data lanes A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a data buffer for each data stream that stores a minima... | 08/09/2011 |
| 7974278 | Packet switch with configurable virtual channels A communication system includes a packet switch that routes data packets between endpoint devices in the communication system through virtual channels. The packet switch includes output ports each having a link bandwidth for outputting data packets. Each virtual cha... | 07/05/2011 |
| 7941723 | Clock generator and method for providing reliable clock signal using array of MEMS resonators A clock generator is disclosed that includes an array of MEMS resonators and a test circuit. The test circuit is operable at start-up to operate one or more of the MEMS resonators to generate test output and analyze the test output to determine whether the operated ... | 05/10/2011 |
| 7940762 | Content driven packet switch A packet switch routes data packets based on both packet headers and data payloads in the data packets. The packet switch receives data packets, identifies a destination port of the packet switch for each data packet based on a packet header of the data packet, and ... | 05/10/2011 |
| 7921400 | Method for forming integrated circuit device using cell library with soft error resistant logic cells A cell library is disclosed that includes soft error resistant logic cells. The soft error resistant logic cells can be used along with memory cells and conventional logic cells to form integrated circuit designs having increased soft error resistance. A method for ... | 04/05/2011 |
| 7916779 | Adaptive decision feedback equalizer for high data rate serial link receiver An adaptive decision feedback equalizer includes a filter module, a compensation module, and a slicer module. The filter module generates a filtered signal by adaptively filtering an input serial data signal to reduce inter-symbol interference in the serial data sig... | 03/29/2011 |
| 7907625 | Power reduction technique for buffered crossbar switch A communication system that includes a packet switch having a buffered crossbar for routing data packets from input ports to output ports of the packet switch. The buffered crossbar stores a data packet received from an input port based on a clock signal of a clock ... | 03/15/2011 |
| 7847404 | Circuit board assembly and packaged integrated circuit device with power and ground channels A packaged integrated circuit device and a circuit board assembly are disclosed that include a semiconductor die and a package substrate that includes a first grid array of contact pads that are electrically coupled to corresponding contact pads on the semiconductor... | 12/07/2010 |
| 7877657 | Look-ahead built-in self tests A method and apparatus are disclosed for predicting the failure of a functional element of an integrated circuit during operation. The method includes determining whether the functional element of the integrated circuit device is in an idle cycle, performing a stres... | 01/25/2011 |
| 7853731 | System and method for embedded displayport link training The method of the present invention includes loading a selected set of preset parameters into a source device and a sink device of the DisplayPort device of an embedded system. Link training is then performed between the source device and the sink device utilizing t... | 12/14/2010 |
| 7827555 | Scheduler for a multiprocessing computing system A system and method for scheduling a thread identifies runnable threads based on precycle signals determined before the scheduling cycle. The thread indexes of the runnable threads are grouped according to the thread priorities of the runnable threads, and the threa... | 11/02/2010 |
| 7817652 | System and method of constructing data packets in a packet switch A packet switch includes a pointer table for mapping locations in an input data buffer to locations in an output data buffer. The processor generates an output data packet based on data portions in the input data buffer and based on the pointer table. The output dat... | 10/19/2010 |
| 7816959 | Clock circuit for reducing long term jitter A clock circuit generates a reference clock signal based on a resonant frequency of a crystal, generates thermometer-coded signals based on the reference clock signal, and generates a pulse train based on the thermometer-coded signals. The pulse train has a frequenc... | 10/19/2010 |
| 7801308 | Secure key encoding for content protection A device and method for protecting HDCP cryptographic keys are presented herein. The device and method include receiving a set of HDCP cryptographic keys, encoding the set of HDCP cryptographic keys such that the resultant encoded cryptographic data is enabled to be... | 09/21/2010 |
| 7800236 | Semiconductor die and method for forming a semiconductor die having power and ground strips that are oriented diagonally A method for forming a semiconductor die and a flip-chip integrated circuit device are disclosed that include a power and ground mesh that is oriented diagonally. A layout of a semiconductor die is formed by generating a first integrated circuit design and copying a... | 09/21/2010 |
| 7796629 | Packet switch with configurable bandwidth allocation precision A packet switch including input ports and output ports allocates an output bandwidth of each output port among virtual channels based on bandwidth allocations values corresponding to the virtual channels and a bandwidth precision value of the output port. The bandwi... | 09/14/2010 |
| 7786763 | Clock circuit with harmonic frequency detector A clock circuit includes a phase-lock loop for generating an output clock signal based on a data signal and a harmonic frequency detector for detecting whether the frequency of the output clock signal is a harmonic frequency of a frequency of a reference clock signa... | 08/31/2010 |
| 7779197 | Device and method for address matching with post matching limit check and nullification A device and method are disclosed for performing a limit address check validation in a switching device. The device includes a data selector circuit that is enabled to select the content of an address register in an array of address registers, and a comparator elect... | 08/17/2010 |
| 7756014 | Device and method for handling catastrophic routing A method and device for handling catastrophic switch routing errors. Upon receiving a communication packet in a packet switching device, a port in the switching device is matched with the destination address of the communication packet and a routing code is generate... | 07/13/2010 |
| 7750618 | System and method for testing a clock circuit A test circuit determines whether a frequency of an output clock signal of a clock circuit is above an output threshold frequency. An input clock signal of the clock circuit is set to an elevated frequency that is higher than a specified frequency. A first counter c... | 07/06/2010 |
| 7747904 | Error management system and method for a packet switch A packet switch includes an error management module in addition to various components that facilitate routing of data packets through the packet switch. The components generate error codes indicating errors occurring in the packet switch and provide the error codes ... | 06/29/2010 |
| 7737739 | Phase step clock generator An integrated circuit includes a phase step generator and a clock circuit. The phase step generator generates an input clock signal based on a reference clock and the clock circuit generates an output clock signal based on the input clock signal. Additionally, the c... | 06/15/2010 |
| 7715377 | Apparatus and method for matrix memory switching element A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is plac... | 05/11/2010 |
| 7714620 | Comparator with amplitude and time hysteresis A comparator generates lower and upper reference voltages to establish an amplitude hysteresis. A first comparator circuit generates a first comparison signal indicating whether an input signal is above the upper reference voltage. A second comparator circuit genera... | 05/11/2010 |
| 7706387 | System and method for round robin arbitration A switch includes an arbiter that receives a plurality of requests from N input ports, and determines N round robin arbitration option winners by performing N round robin arbitration options on the requests, each of the N round robin arbitration options performed as... | 04/27/2010 |
| 7706113 | Electrical overstress (EOS) and electrostatic discharge (ESD) protection circuit and method of use A system and method are provided for electrostatic discharge (ESD) protection circuit having overshoot and undershoot voltage protection during a power supply ramp-up of the circuit. In a specific embodiment, the ESD protection circuit of the present invention inclu... | 04/27/2010 |
| 7694025 | Method and device for base address sorting and entry into base address registers A base address sorting device in a serial switch is disclosed which includes an array of shadow registers, each shadow register in the array being electrically coupled to a base address register, in an array of base address registers, each of the base address regist... | 04/06/2010 |
| 7693040 | Processing switch for orthogonal frequency division multiplexing A baseband processor includes a processing switch for performing orthogonal frequency division multiplexing operations on data packets and routing the data packets in the baseband processor. Additionally, the baseband processor includes digital signal processors for... | 04/06/2010 |
| 7684431 | System and method for arbitration in a packet switch A packet switch arbitration system and method for arbitration in a packet switch. In one aspect, a method of issuing grants to an ingress port is disclosed in which a first grant request and burst signal are activated at an ingress port having more than one word ava... | 03/23/2010 |
| 7683720 | Folded-cascode amplifier with adjustable continuous time equalizer A system and method are provided for a folded cascode amplifier circuit that includes a first order high-pass filter coupled to a first bias voltage, a first input signal and a second input signal, the first input signal and the second input signal defining a differ... | 03/23/2010 |
