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| Number | Title | Issue Date |
| 8185896 | Method for data processing using a multi-tiered full-graph interconnect architecture A method is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The p... | 05/22/2012 |
| 8181131 | Enhanced analysis of array-based netlists via reparameterization A mechanism is provided for increasing the scalability of formal verification solutions through enabling the use of input reparameterization on logic models that include memory arrays. A pre-processing mechanism enables the selection of a cut-based design partition ... | 05/15/2012 |
| 8176026 | Consolidating file system backend operations with access of data Mechanisms for performing a backend operation in a file system are provided. A backend operation on a portion of the file system is initiated. At least one indirect transition table data structure is created for performing the backend operation. Metadata correspondi... | 05/08/2012 |
| 8166249 | Performing a least recently used (LRU) algorithm for a co-processor A method to perform a least recently used (LRU) algorithm for a co-processor is described, which co-processor in order to directly use instructions of a core processor and to directly access a main storage by virtual addresses of said core processor comprises a TLB ... | 04/24/2012 |
| 8161493 | Weighted-region cycle accounting for multi-threaded processor cores An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to... | 04/17/2012 |
| 8158461 | Continuously referencing signals over multiple layers in laminate packages A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the... | 04/17/2012 |
| 8156287 | Adaptive data prefetch A data processing system includes a processor, a unit that includes a multi-level cache, a prefetch system and a memory. The data processing system can operate in a first mode and a second mode. The prefetch system can change behavior in response to a desired power ... | 04/10/2012 |
| 8146034 | Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays. The mechanism includes an array merging component to optimally merge an array output such that if the addre... | 03/27/2012 |
| 8145887 | Enhanced load lookahead prefetch in single threaded mode for a simultaneous multithreaded microprocessor A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. A processing unit detects if a long-latency miss associated with a load instruction has been encountered. Responsive to a long-latency ... | 03/27/2012 |
| 8145723 | Complex remote update programming idiom accelerator A remote update programming idiom accelerator is configured to detect a complex remote update programming idiom in an instruction sequence of a thread. The complex remote update programming idiom includes a read operation for reading data from a storage location at ... | 03/27/2012 |
| 8140936 | System for a combined error correction code and cyclic redundancy check code for a memory channel A memory system is provided that performs error correction at a memory device level. The memory system comprises a memory hub device integrated in the memory module and a link interface integrated in the memory hub device that provides a communication pathway betwee... | 03/20/2012 |
| 8140902 | Internally controlling and enhancing advanced test and characterization in a multiple core microprocessor A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time needed to test a multiple core chip, the mechanism uses micro-architectural support that allows one core, a co... | 03/20/2012 |
| 8140765 | Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store req... | 03/20/2012 |
| 8140756 | Information handling system with immediate scheduling of load operations and fine-grained access to cache memory An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store req... | 03/20/2012 |
| 8140731 | System for data processing using a multi-tiered full-graph interconnect architecture A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The p... | 03/20/2012 |
| 8135910 | Bandwidth of a cache directory by slicing the cache directory into two smaller cache directories and replicating snooping logic for each sliced cache directory A cache, system and method for improving the snoop bandwidth of a cache directory. A cache directory may be sliced into two smaller cache directories each with its own snooping logic. By having two cache directories that can be accessed simultaneously, the bandwidth... | 03/13/2012 |
| 8131976 | Tracking effective addresses in an out-of-order processor Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective ad... | 03/06/2012 |
| 8127300 | Hardware based dynamic load balancing of message passing interface tasks Mechanisms for providing hardware based dynamic load balancing of message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait per... | 02/28/2012 |
| 8122410 | Specifying and validating untimed nets In accordance with an aspect of the present invention, specifying a portion of a circuit design to be treated as untimed by static timing analysis is performed on the RTL design by means of an attribute annotation. The process is operable to map through to the Physi... | 02/21/2012 |
| 8122312 | Internally controlling and enhancing logic built-in self test in a multiple core microprocessor A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while a... | 02/21/2012 |
| 8122222 | Access speculation predictor with predictions based on a scope predictor An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the ... | 02/21/2012 |
| 8122167 | Polling in a virtualized information handling system A software thread is dispatched for causing the system to poll a device for determining whether a condition has occurred. Subsequently, the software thread is undispatched and, in response thereto, an interrupt is enabled on the device, so that the device is enabled... | 02/21/2012 |
| 8108655 | Selecting fixed-point instructions to issue on load-store unit Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In t... | 01/31/2012 |
| 8108545 | Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture A mechanism is provided for packet coalescing in virtual channels of a data processing system. A first processor bundles original data into a data packet to be transmitted to a destination processor, the original data comprising payload data and overhead data. The f... | 01/31/2012 |
| 8099582 | Tracking deallocated load instructions using a dependence matrix A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of the load instruction, an instruction scheduler allocates the load instru... | 01/17/2012 |
| 8086936 | Performing error correction at a memory device level that is transparent to a memory channel A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device.... | 12/27/2011 |
| 8086826 | Dependency tracking for enabling successive processor instructions to issue An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions alo... | 12/27/2011 |
| 8086801 | Loading data to vector renamed register from across multiple cache lines A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation re... | 12/27/2011 |
| 8082482 | System for performing error correction operations in a memory hub device of a memory module A memory system is provided for performing error correction operations in a memory module. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises a... | 12/20/2011 |
| 8082315 | Programming idiom accelerator for remote update A remote update programming idiom accelerator identifies a remote update programming idiom in an instruction sequence of a thread running on a processing unit of a data processing system. The remote update programming idiom includes a read operation for reading data... | 12/20/2011 |
| 8077602 | Performing dynamic request routing based on broadcast queue depths Mechanisms for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips ... | 12/13/2011 |
| 8055477 | Identifying deterministic performance boost capability of a computer system A benchmark tester retrieves a voltage margin that corresponds to a device that a system includes. The voltage margin indicates an additional amount of voltage to apply to a nominal voltage that, when added, results in the device operating at a power limit while exe... | 11/08/2011 |
| 8041928 | Information handling system with real and virtual load/store instruction issue queue An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real... | 10/18/2011 |
| 8037366 | Issuing instructions in-order in an out-of-order processor using false dependencies A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes a tag register to determine whether a previous tag associated with a ... | 10/11/2011 |
| 8019919 | Method for enhancing the memory bandwidth available through a memory module A method for enhancing the memory bandwidth available through a memory module of a memory system is provided. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in ... | 09/13/2011 |
| 8014387 | Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture A mechanism is provided for transmitting data from a first processor of a data processing system to a second processor of the data processing system. In one or more switches, a set of virtual channels is created, the one or more switches comprising, for each process... | 09/06/2011 |
| 8009672 | Apparatus and method of splitting a data stream over multiple transport control protocol/internet protocol (TCP/IP) connections A method, system and apparatus for improving data transfer rate over a network are provided. When a piece of data is to be transmitted to a target system, it is divided into a number of packets and a determination is made as to whether the number of packets exceeds ... | 08/30/2011 |
| 7979732 | Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock contr... | 07/12/2011 |
| 7969451 | Method and apparatus for dynamically sizing color tables A method, apparatus, and computer instructions for storing colors in a color table used in displaying graphics in a data processing system. A request for a color map is received, wherein the request includes a number of entries for the color map. A color map locatio... | 06/28/2011 |
| 7961025 | Current-mode phase rotator with partial phase switching In one illustrative embodiment, an apparatus for a current-mode phase rotator with partial input phase switching comprises a mixer, wherein the mixer is a four quadrant current-mode mixer comprised of four interpolation buffers, wherein each interpolation buffer rec... | 06/14/2011 |
