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An armor with rollers is provided that enables a user to move in all positions by rolling on a hard and smooth surface while constantly varying his bearing points on the ground.
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| Number | Title | Issue Date |
| 5605724 | Method of forming a metal conductor and diffusion layer A method for minimizing reaction between metal conductors and other metals to minimize change in sheet resistance of the conductors upon heat treatment which includes providing a substrate. The substrate is preferably one of a dielectric, a metal or a sem... | 02/25/1997 |
| 5596286 | Current limiting devices to reduce leakage, photo, or stand-by current in an integrated circuit A current limiting circuit 12 is placed between a supply voltage, Vcc and circuitry 14. Current limiting circuit 12 supplies sufficient current for normal operation of circuitry 14, but less than would be required if all potentially conductive paths of ci... | 01/21/1997 |
| 5593924 | Use of a capping layer to attain low titanium-silicide sheet resistance and uniform silicide thickness for sub-micron silicon and polysilicon lines A titanium-silicide process using a capping layer to reduce the silicide sheet resistance. A layer of titanium (20) is deposited. A react capping layer (22) may then be deposited to prevent contaminants from entering the titanium layer (20)during the subs... | 01/14/1997 |
| 5593905 | Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as... | 01/14/1997 |
| 5589695 | High-performance high-voltage device structures An improved high-voltage device structure (10, 50, or 60) is a hybrid silicon-based/non-silicon-based power device that has a low Rds(on) relative to devices formed using only a silicon substrate and includes control circuit (14, 14' or 14") fo... | 12/31/1996 |
| 5525780 | Method and apparatus for uniform semiconductor material processing using induction heating with a chuck member A multipurpose chuck apparatus (100) has a chamber (112) for holding a medium (114). The medium (114) is heated into a high temperature molten state by a radio frequency induction heating coil (130). The medium (114) heats up a semiconductor material (118... | 06/11/1996 |
| 5517051 | Silicon controlled rectifier structure for electrostatic discharge protection A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conduct... | 05/14/1996 |
| 5515292 | Circuit activity driven state assignment of FSMS implemented in CMOS for low power reliable operations A method for optimizing a circuit containing a finite state machine (FSM) based on transition density. A first state assignment is assigned for each state. Then, a first transition density characteristic associated with the first state assignment is deter... | 05/07/1996 |
| 5506158 | BiCMOS process with surface channel PMOS transistor A BiCMOS device 10 having a bipolar transistor 60, a PMOS transistor 64 and a p-type polysilicon resistor 70. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. PMOS transistor 64 ... | 04/09/1996 |
| 5502330 | Stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as... | 03/26/1996 |
| 5498882 | Efficient control of the body voltage of a field effect transistor Efficient control of the body voltage embodiment, the body node of a first field effect transistor is connected to the gate of the first transistor through a second field effect transistor. In another embodiment, the body node (p-) of a first transistor i... | 03/12/1996 |
| 5494526 | Method for cleaning semiconductor wafers using liquified gases A semiconductor processing system (10) is provided that comprises a cleaning chamber (12) and a load lock wafer handler chamber (14). A cleaning agent (34) is placed in a cleaning bath chamber (28). A semiconductor substrate (16) is placed in contact with... | 02/27/1996 |
| 5493133 | PNP punchthrough-assisted protection device for special applications in CMOS technologies A protection circuit (40) providing positive and negative stress protection. A lateral PIN (58) assists in the triggering of a silicon-controlled rectifier (60) for positive stress protection. A vertical PNP (62) provides negative stress protection. A Sch... | 02/20/1996 |
| 5488317 | Wired logic functions on FPGA's An FPGA having a plurality of logic modules with configurable output drivers (8) to enable outputs (y) of several logic modules to be wired together. The output driver (8) comprises a n-channel and a p-channel driver transistor (16, 20) which are connecte... | 01/30/1996 |
| 5488315 | Adder-based base cell for field programmable gate arrays An adder-based base cell (10) is provided for field programmable gate arrays. The base cell (10) includes a first inverter (13) operable to receive a first input signal (A). A first NAND gate (12) is coupled to the first inverter (13) and is operable to r... | 01/30/1996 |
| 5486484 | Lateral power MOSFET structure using silicon carbide A MOSFET device (100) having a silicon carbide substrate (102). A channel region (106) of a first conductivity type and an epitaxial layer (104) of a second conductivity type are located above the silicon carbide substrate (102). First and second source/d... | 01/23/1996 |
| 5487017 | Circuit activity driven multilevel logic optimization for low power reliable operation A method and apparatus for optimizing a boolean network. The boolean network contains a plurality of functions and a plurality of nodes. Any cube-free divisors (a divisor in which no cube divides the divisor evenly) in the boolean network which apply to a... | 01/23/1996 |
| 5483636 | Automated diagnosis using wafer tracking databases A system and method for isolating one or more causes of wafer misprocessing. A list of interesting queries (10) is generated. During wafer processing (15), processing parameters are measured (20) and a wafer tracking database (25) is created. The list of ... | 01/09/1996 |
| 5477151 | Capacitor and diode circuitry for on chip power spike detection A memory cell system with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detect... | 12/19/1995 |
| 5473334 | Polarized antenna having longitudinal shunt slotted and rotational series slotted feed plates An antenna for transmitting rf energy. A polarizer for selectively polarizing the rf energy is operatively connected to a longitudinal shunt slotted plate for radiating rf energy therethrough. A rotational series slotted plate is operatively connected to ... | 12/05/1995 |
| 5469065 | On chip capacitor based power spike detection A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturba... | 11/21/1995 |
| 5468676 | Trench isolation structure and method for forming An isolation structure is disclosed which isolates an active region (24) from other proximate active regions. The isolation structure utilizes the combination of a LOCOS structure (26) comprising bird's beak structure (26a) and (26b). A trench (34) is for... | 11/21/1995 |
| 5468667 | Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A f... | 11/21/1995 |
| 5468666 | Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at a first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second d... | 11/21/1995 |
| 5464499 | Multi-electrode plasma processing apparatus A multi-electrode plasma processing system (10) provides flexible plasma processing capabilities for semiconductor device fabrication. The plasma processing equipment (10) includes a gas showerhead assembly (52) a radio-frequency chuck (24), and screen el... | 11/07/1995 |
| 5453124 | Programmable multizone gas injector for single-wafer semiconductor processing equipment A programmable multizone fluids injector for use in single-wafer semiconductor processing equipment including an injector having a plurality of orifices therein which are divided into a number of separate zones or areas. These zones or areas are connected... | 09/26/1995 |
| 5453384 | Method of making a silicon controlled rectifier device for electrostatic discharge protection A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conduct... | 09/26/1995 |
| 5451810 | Metal-to-metal antifuse structure A method of forming a metal-to-metal antifuse. An antifuse stack 32 is formed comprising a first metal layer 16, an antifuse dielectric layer, and an etchstop layer. The etchstop layer may, for example, comprise an oxide layer 24 and an amorphous silicon ... | 09/19/1995 |
| 5450267 | ESD/EOS protection circuits for integrated circuits An ESD/EOS protection circuit 10. Trigger nMOS transistor M1 has a drain 20 connected to a voltage pad 22, a gate 24 connected to ground 26 and a source 28 connected to ground 26 through source resistor Re. Switch control nMOS transistor M2 has... | 09/12/1995 |
| 5448081 | Lateral power MOSFET structure using silicon carbide A MOSFET device (100) having a silicon carbide substrate (102). A channel region (106) of a first conductivity type and an epitaxial layer (104) of a second conductivity type are located above the silicon carbide substrate (102). First and second source/d... | 09/05/1995 |
| 5447875 | Self-aligned silicided gate process A method of forming a self-aligned silicided gate (44) in a semiconductor device (10). A gate electrode having a conductive body (22) and a disposable cap (24) is formed on the surface of the semiconductor body. A sidewall spacer (32) is formed on the sid... | 09/05/1995 |
| 5446825 | High performance multi-zone illuminator module for semiconductor wafer processing A high-performance multi-zone illuminator module (130) for directing optical energy onto a semiconductor wafer (60) in a device fabrication reactor to improve overall semiconductor wafer processing uniformity comprises a housing connectable to the wafer p... | 08/29/1995 |
| 5444815 | Multi-zone lamp interference correction system A multi-zone lamp interference correction system and method for accurate pyrometry-based multi-point wafer temperature measurement in a multi-zone rapid thermal processing system comprises a plurality of lamps arranged in zones. A dummy lamp is also provi... | 08/22/1995 |
| 5443315 | Multi-zone real-time emissivity correction system A multi-zone emissivity correction system and method that may be used in a multi-zone illuminator of a RTP-AVP system. The multi-zone illuminator comprises a plurality of lamps arranged in zones. A dummy lamp is also provided for each zone. A first plural... | 08/22/1995 |
| 5441903 | BiCMOS process for supporting merged devices A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. Emitter elec... | 08/15/1995 |
| 5438548 | Synchronous memory with reduced power access mode The synchronous memory (30) includes an address transition detection and control circuitry (42) which detects whether a net change in a selected portion of the address has occurred between consecutive active edges of the clock signal. If an address transi... | 08/01/1995 |
| 5436173 | Method for forming a semiconductor on insulator device A method for forming a semiconductor on insulator device is provided that begins with an outer semiconductor layer (16). Trenches (12) of a predetermined depth are formed in outer semiconductor layer (16). An insulator layer (20) is formed outwardly from ... | 07/25/1995 |
| 5426614 | Memory cell with programmable antifuse technology A memory cell (10) comprising a first antifuse (A1) operable to place the memory cell (10) in a non-volatile state. In one embodiment, the memory cell (10) comprises a pair of cross-coupled inverters (I1,I2). The first antifuse (A1)is connected between an... | 06/20/1995 |
| 5420056 | Junction contact process and structure for semiconductor technologies A device and method for forming an improved junction contact in a semiconductor device (10). A portion of an interlevel dielectric layer (28) is etched away to expose a surface of at least one junction region (26). Next, a dielectric layer is formed over ... | 05/30/1995 |
| 5406110 | Resurf lateral double diffused insulated gate field effect transistor A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) t... | 04/11/1995 |
