Garner; Jacqueline J., Brady, III; Wade James, Telecky, Jr.; Frederick J. - US Patent Attorneys and Agents

Attorney: Garner; Jacqueline J., Brady, III; Wade James, Telecky, Jr.; Frederick J.

Number of patents: 35
Last date: May 13, 2003

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Number	Title	Issue Date
6561868	System and method for controlling a polishing machine A system for controlling a polishing machine during polishing of a workpiece, such as a semiconductor wafer, includes a carrier which has an interface surface for engaging a workpiece and establishing ultrasonic coupling thereto. At least one crystal osci...	05/13/2003
6555446	Body contact silicon-on-insulator transistor and method A method for fabricating a body contact silicon-on-insulator transistor (10) includes forming a semiconductor substrate (12) over an insulator (14) and lightly doping the semiconductor substrate (12) to form a body region (18). The method also includes fo...	04/29/2003
6539526	Method and apparatus for determining capacitances for a device within an integrated circuit An integrated circuit (10) includes a device such as a transistor. A layout (90) of the device is prepared, which in the case of the transistor includes a ground plane section (52), spaced diffusion sections (56A-56B) and a gate section (57). In order to ...	03/25/2003
6488037	Programmable physical action during integrated circuit wafer cleanup Wafer cleaning systems (10, 25) utilizing both chemical and physical action to clean integrated circuit wafers (14, 24) is disclosed. Chemical cleaning action is provided by liquid retained within a tank (2, 22), sized either to hold a single wafer (24) o...	12/03/2002
6482713	Shot averaging for fine pattern alignment with minimal throughput loss A way to average alignment measurements that obtains the advantage of multiple alignment marks per shot without requiring actual measurement of all alignment marks on all wafers of a batch. All alignment marks on all sampled shots are measured and average...	11/19/2002
6436746	Transistor having an improved gate structure and method of construction A method of fabricating an improved gate structure that may be used in a transistor. A primary insulation layer (22) may be formed adjacent a substrate (12). A disposable gate (24) may be formed adjacent the primary insulation layer (22). An isolation die...	08/20/2002
6388288	Integrating dual supply voltages using a single extra mask level Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifica...	05/14/2002
6342420	Hexagonally symmetric integrated circuit cell An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nod...	01/29/2002
6331492	Nitridation for split gate multiple voltage devices A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface, exposing the surface of the oxide layer (12) to a nitrogen ion containin...	12/18/2001
6326293	Formation of recessed polysilicon plugs using chemical-mechanical-polishing (CMP) and selective oxidation A plug is formed of polysilicon, or other oxidizable conductor. Chemical-mechanical polishing is performed, with a polish stop layer defining the top of the dielectric layer. The upper portion of the polysilicon is oxidized to a controlled depth, then the...	12/04/2001
6316829	Reinforced semiconductor package A reinforced semiconductor package (20,30) and method utilizes at least one of the grooves (15,16) and ridges (24,25) formed on the package body (17,23) to reinforce the package body (17,23) to prevent warping of the package after molding....	11/13/2001
6306725	In-situ liner for isolation trench side walls and method An isolation trench (60) comprising a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A layer (50) of an insulation material may be formed over the barrier layer (22). A high density layer (55) o...	10/23/2001
6235612	Edge bond pads on integrated circuits The invention is to a device and the method of making circuit devices with side wall contacts produced on a semiconductor wafer (30) by forming grooves (33,34) partially through the wafer surface to provide a plurality of device elements (32) on a common ...	05/22/2001
6235581	Floating gate memory structure and method for forming a low resistance continuous source line The invention comprises a floating gate memory structure, a method for making a floating gate memory structure, and a method for forming a continuous source line in a floating gate memory structure. One aspect of the invention is a method for forming a co...	05/22/2001
6232644	Oxide profile modification by reactant shunting A method of fabricating a semiconductor device and the device which includes initially providing a layer of silicon having a thin oxide layer thereon and a patterned layer of a masking material not permeable to at least selected oxygen-bearing species and...	05/15/2001
6222251	Variable threshold voltage gate electrode for higher performance mosfets A transistor is formed on the substrate (10) with a graded doping profile for the gate electrode (22). This graded profile is performed for an N-channel transistor by depositing the gate electrode with two separate layers of material. The first layer is a...	04/24/2001
6222228	Method for reducing gate oxide damage caused by charging A method of processing wafers containing a gate oxide assembly (10) is disclosed that reduces gate oxide damage during wafer production due to damage caused by charging. The method comprises creating an oxide gate assembly (10) on a silicon layer (11) in ...	04/24/2001
6218218	Method for reducing gate oxide damage caused by charging A method of processing wafers containing a gate oxide assembly (10) is disclosed that reduces gate oxide damage during wafer production due to damage caused by charging. The method comprises creating an oxide gate assembly (10) on a silicon layer (11) in ...	04/17/2001
6208151	Method and apparatus for measurement of microscopic electrical characteristics The improved method for microscopic measurement of electrical characteristics comprises a standard atomic force microscope (AFM). The AFM includes a pointed, conductively coated tip attached to one end of a softly compliant cantilever arm, also capable of...	03/27/2001
6194313	Method for reducing recess for the formation of local interconnect and or plug trench fill for etchback process A method to reduce the effective recess in conductive plugs 220 by performing an oxide etch or oxide CMP, selective to the conductive material in question. This method can be used for any conductive plug 220 (e.g. aluminum, tungsten, copper, titanium nitr...	02/27/2001
6194280	Method for forming a self-aligned BJT emitter contact A bipolar transistor includes a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, and a base link-up region within the collector region between the intrinsic base region and the e...	02/27/2001
6194267	Integrated circuit having independently formed array and peripheral isolation dielectrics The invention comprises a method of forming an integrated circuit, the method comprising: (1) forming a first dielectric layer disposed outwardly from a semiconductor substrate; (2) forming a first intermediate structure outwardly from the a dielectric la...	02/27/2001
6193068	Containment device for retaining semiconductor wafers A containment device for retaining semiconductor wafers (54) is disclosed. The containment device comprises a first housing member (10) having a frame (12), an inner wall (14) and an outer wall (16). The inner wall (14) and outer wall (16) each extend gen...	02/27/2001
6160290	Reduced surface field device having an extended field plate and method for forming the same A semiconductor device (10) comprises a reduced surface field (RESURF) implant (14). A field oxide layer (20), having a length, is formed over the RESURF implant (14). A field plate (12) extends from a near-side of the field oxide layer (20) and over at l...	12/12/2000
6159835	Encapsulated low resistance gate structure and method for forming same An encapsulated gate structure includes a polysilicon layer, a barrier layer overlying the polysilicon layer and having opposing sidewalls, a metal layer overlying the barrier layer and having opposing sidewalls, a top dielectric layer overlying the metal...	12/12/2000
6157062	Integrating dual supply voltage by removing the drain extender implant from the high voltage device A dual voltage chip is fabricated with no intermediate-doped (LDD or MDD) area in the high-voltage transistors by adjusting the gate sidewall spacer thickness and the source/drain implant....	12/05/2000
6147384	Method for forming planar field effect transistors with source and drain an insulator and device constructed therefrom A method of forming a field effect transistor with source and drain on an insulator includes forming a first void region (11) in the outer surface of a semiconductor body (10) and forming a second void region (11) in the outer surface of a semiconductor b...	11/14/2000
6143614	Monolithic inductor The monolithic inductor (30) includes a substrate (38), a spiral metal trace (32) disposed insulatively above the substrate (38), where a parasitic capacitance (56) is generated between the spiral metal trace (32) and the substrate (38), and a depletion l...	11/07/2000
6140024	Remote plasma nitridation for contact etch stop A method is disclosed of nitridating an oxide layer (12) to form a stop layer for selective etching of sacrificial layer comprising the steps of, obtaining a wafer (10), forming a gate (30) on the wafer (10), depositing an oxide layer (12) on the wafer (1...	10/31/2000
6130144	Method for making very shallow junctions in silicon devices A processing method for forming very shallow junctions 25 utilizing the differential diffusion coefficients of impurity dopants 38 in germanium as compared to silicon to confine the dopants 38 to very shallow regions made of substantially pure germanium 3...	10/10/2000
6114733	Surface protective layer for improved silicide formation Method of fabricating a narrow linewidth transistor having a low sheet resistance. The transistor may be fabricated in a surface of a semiconductor layer (12). A gate body (14) may be formed separated from an outer surface (16) of the semiconductor layer ...	09/05/2000
6063670	Gate fabrication processes for split-gate transistors A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A first gate dielectric (20) is formed. Next, a disposable layer (22) is formed over the first...	05/16/2000
6057214	Silicon-on-insulation trench isolation structure and method for forming A silicon-on-insulator trench isolation structure is disclosed that includes an active silicon-on-insulator region, an active bulk substrate region, and a trench region positioned between the active silicon-on-insulator region and the active bulk substrat...	05/02/2000
6046113	Combined dry and wet etch for improved silicide formation A method of removing an outer layer from an inner surface during semiconductor fabrication. A portion of the outer layer (50) may be anisotropically etched. A remaining portion of the outer layer (55) may then be wet etched without impairing the inner sur...	04/04/2000
6043535	Self-aligned implant under transistor gate The invention comprises a transistor having a self-aligned implant under the gate. The transistor comprises a drain region, a source region opposite the drain region, and a channel region in a semiconductor substrate extending between the source region an...	03/28/2000

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Attorney: Garner; Jacqueline J., Brady, III; Wade James, Telecky, Jr.; Frederick J.