Garner; Jacqueline J., Brady, III; W. James, Telecky, Jr.; Frederick J. - US Patent Attorneys and Agents

Attorney: Garner; Jacqueline J., Brady, III; W. James, Telecky, Jr.; Frederick J.

Number of patents: 131
Last date: February 10, 2004

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Number	Title	Issue Date
6687973	Optimized metal fuse process A metal fuse process that uses a thinner (e.g., 6000 Å) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for testing but is not removed over the fuses (104). Because the oxide (108) is thin at the upper co...	02/10/2004
6686236	Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resista...	02/03/2004
6607985	Gate stack and etch process A five step, low pressure, high-density-plasma etch process used to etch complicated DRAM transistor gate stacks with high inter-layer selectivity. Such stacks typically consist of the following layers: silicon nitride (310), tungsten (320), titanium nitr...	08/19/2003
6605859	Buried Zener diode structure and method of manufacture A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface....	08/12/2003
6605536	Treatment of low-k dielectric films to enable patterning of deep submicron features Treating a low-k dielectric layer (104) using a highly oxidizing wet solution (e.g., H2 SO4) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130,132). The w...	08/12/2003
6599802	Low-voltage-Vt (CMOS) transistor design using a single mask and without any additional implants by way of tailoring the effective channel length (Leff) Low threshold voltage transistors are fabricated by removing oxide spacers from the poly gate sidewalls of the transistors that are to be low threshold voltage. This causes the effective channel length of the low Vt transistors to be shorter than that of ...	07/29/2003
6590798	Apparatus and methods for imprint reduction for ferroelectric memory cell Memory devices and methods are disclosed for reading a restoring data from and to ferroelectric memory cells, wherein a data bit is sensed from a data memory cell, a toggle bit is sensed from a toggle memory cell, and the sensed data bit is transferred to...	07/08/2003
6587367	Dummy cell structure for 1T1C FeRAM cell array A ferroelectric memory structure is described for the 1T1C arrangement in ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplif...	07/01/2003
6586839	Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers A conductive via pattern (110) between the uppermost metal interconnect layer (Mn) and next underlying metal interconnect layer (Mn-1) in the bond pad areas strengthens the interlevel dielectric (ILD3) between metal layers (Mn	07/01/2003
6586334	Reducing copper line resistivity by smoothing trench and via sidewalls A method of fabricating an integrated circuit. A thin liner (110, 210, 310) is deposited over dielectric layer including within a trench (108) and/or via (106). The thin liner (110, 210, 310) smoothes the sidewalls of the trench (108) and/or via (106) and...	07/01/2003
6586267	Transient fuse for charge-induced damage detection A transient fuse (102) and antenna (110) for detecting charge-induced plasma damage in a device (112). When the transient fuse (102) is placed between the antenna (110) and the device (112), only charge-induced damage during a metal clear portion of an et...	07/01/2003
6583427	Extended life source arc chamber liners A liner (102) for an arc chamber (100) of an ion implanter. The arc chamber (100) comprises a liner (102) on the inner surface (104) of the arc chamber (100) that extends the life of the arc chamber (100). The liner (102) comprises a one piece portion (10...	06/24/2003
6583053	Use of a sacrificial layer to facilitate metallization for small features A method of fabricating a copper interconnect using a sacrificial layer. A SiC layer (106) is formed over the dielectric layer (102). A sacrificial layer (108) is formed over the SiC layer (106). A trench (112) is etched in the sacrificial layer (108), th...	06/24/2003
6582977	Methods for determining charging in semiconductor processing Methods are disclosed for determining charging related to one or more semiconductor processing steps. A wafer having a substantially unpolarized ferroelectric capacitor formed therein is exposed to a processing operation. After processing, the ferroelectr...	06/24/2003
6579798	Processes for chemical-mechanical polishing of a semiconductor wafer A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a por...	06/17/2003
6579770	Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled po...	06/17/2003
6576922	Ferroelectric capacitor plasma charging monitor Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of intere...	06/10/2003
6576482	One step deposition process for the top electrode and hardmask in a ferroelectric memory cell One aspect of the invention relates to a one-step process for forming a transition metal aluminum oxynitride layer over a transition metal aluminum nitride layer. The transition metal aluminum nitride layer is sputter deposited using a transition metal/al...	06/10/2003
6574135	Shared sense amplifier for ferro-electric memory cell A ferro-electric memory device system and method is described for accessing and sensing memory cells of an FeRAM memory array with an open bit line architecture. The memory device permits the sharing of certain memory circuits such as, a sense amplifier, ...	06/03/2003
6573549	Dynamic threshold voltage 6T SRAM cell An embodiment of the instant invention is a memory device comprising: a memory cell including: a first transistor (108 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of...	06/03/2003
6573194	Method of growing surface aluminum nitride on aluminum films with low energy barrier An integrated circuit having an interconnect layer (104) that comprises a first barrier layer (106) and an aluminum-based layer (108) overlying the first barrier layer (106). An aluminum-nitride layer (112) is located on the surface of the aluminum-based ...	06/03/2003
6573167	Using a carbon film as an etch hardmask for hard-to-etch materials A carbon hardmask (122) for etching hard-to-etch materials (110/112/114) such as Pt, Ir, Ru, IrO2, RuO2, BST, PZT, SBT, FeNi, and FeNiCo and other used in DRAMs, FeRAMs, and magnetic storage devices. Chemically assisted physical sput...	06/03/2003
6569741	Hydrogen anneal before gate oxidation A process for preparing a silicon surface for gate dielectric formation. The silicon is annealed in a hydrogen ambient prior to gate dielectric formation. The gate dielectric is then formed, along with other layers of the gate structure. The channel is th...	05/27/2003
6566211	Surface modified interconnects An interconnect structure having refractory sidewalls 240 for enhanced yield, performance and reliability. The primary purpose of the refractory metal 240 is to getter sidewall impurities, residual polymers, and corrosive species by-products from the plas...	05/20/2003
6566200	Flash memory array structure and method of forming A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second...	05/20/2003
6562724	Self-aligned stack formation A method to simplify the polycide gate structure fabrication processes by using a hardmask 240 to define a pattern of siliciding 260 a silicon layer 230, and then using the silicide 260 to mask removal of the unreacted silicon 220 and 230 in locations whe...	05/13/2003
6559050	Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSiY NZ) region providing the interface between the tungsten conducting plug a...	05/06/2003
6551943	Wet clean of organic silicate glass films A post-etch clean up process for OSG. After the trench (112)/via (114) etch in a dual damascene process, a wet chemistry comprising HF and H2 O2 is used to remove residues without etching or damaging the OSG film in the ILD (108) or ...	04/22/2003
6545903	Self-aligned resistive plugs for forming memory cell with phase change material Memory devices are disclosed for storage and retrieval of information, wherein resistive plugs are provided above and below a phase change material to form a memory cell. The plugs may be formed by implanting regions in high resistivity material above and...	04/08/2003
6544886	Process for isolating an exposed conducting surface A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (...	04/08/2003
6531355	LDMOS device with self-aligned RESURF region and method of fabrication A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and proces...	03/11/2003
6528386	Protection of tungsten alignment mark for FeRAM processing A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom e...	03/04/2003
6514881	Hybrid porous low-K dielectrics for integrated circuits An organically modified dielectric network structure (208) and solid halide-containing material (206) are co-deposited using a chemical vapor deposition process. The solid halide-containing material (206) is then sublimated leaving a porous dielectric (21...	02/04/2003
6503838	Integrated circuit isolation of functionally distinct RF circuits A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including forming a portion of an isolation region to expose a first area of the substrate, depositing a mask layer over ...	01/07/2003
6501152	Advanced lateral PNP by implant negation A lateral NPN transistor (LPNP) (102) having the lightly doped drain extension implant blocked from the emitter region (118) but not the collector region (120). Accordingly, the emitter region (118) has a more abrupt junction for high emitter injection ef...	12/31/2002
6500678	Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resista...	12/31/2002
6497824	One mask solution for the integration of the thin film resistor A method for integrating a thin film resistor (60) into an interconnect process flow. Metal interconnect lines (40) are formed over a semiconductor body (10). An interlevel dielectric (50) is then formed over the metal interconnect lines (40). Conductivel...	12/24/2002
6483149	LDMOS device with self-aligned resurf region and method of fabrication A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and proces...	11/19/2002
6482688	Utilizing amorphorization of polycrystalline structures to achieve T-shaped MOSFET gate A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises...	11/19/2002
6469353	Integrated ESD protection circuit using a substrate triggered lateral NPN An ESD protection circuit (100) and method is described herein. A lateral npn transistor (104) is connected between an I/O pad (110) and ground (GND). A substrate biasing circuit (150) increases the voltage across a substrate resistance (114) during an ES...	10/22/2002

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Attorney: Garner; Jacqueline J., Brady, III; W. James, Telecky, Jr.; Frederick J.