Garner; Jacqueline J. - US Patent Attorneys and Agents

Attorney: Garner; Jacqueline J.

Number of patents: 334
Last date: May 22, 2012

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Number	Title	Issue Date
8183137	Use of dopants to provide low defect gate full silicidation The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the la...	05/22/2012
8183117	Device layout in integrated circuits to reduce stress from embedded silicon-germanium An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-...	05/22/2012
8154101	High voltage diode with reduced substrate injection A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is pre...	04/10/2012
8138532	Pin photodiode and manufacturing method of same The objective of this invention is to provide a semiconductor device containing a photodiode and having stable, high sensitivity with respect to short wavelength light near 405 nm, and a manufacturing method for said semiconductor device. PIN photodiode (100C...	03/20/2012
8138074	ICs with end gates having adjacent electrically connected field poly A method of forming an IC includes forming a first and a second gate portion using a poly mask. The first portion includes a first active poly gate having a line width W1 over an end of a first active area framed by a first active area edge and a first ad...	03/20/2012
8134382	Semiconductor wafer having scribe line test modules including matching portions from subcircuits on active die A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arrang...	03/13/2012
8134212	Implanted well breakdown in high voltage devices An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed by implanting n-type dopants into a p-type IC substrate in addition to a conventional n-type buried layer (...	03/13/2012
8134204	DEMOS transistors with STI and compensated well in drain A drain extended MOS (DEMOS) transistor with an element of field oxide separating the drain contact from the gate, and a compensation region of opposite polarity in the drain under the gate, is disclosed. The inventive DEMOS may be fabricated in a CMOS IC without ad...	03/13/2012
8129248	Method of producing bipolar transistor structures in a semiconductor process In the method of producing bipolar transistor structures in a semiconductor process, an advanced epitaxial trisilane process can be used without the risk of poly stringers being formed. A base window is structured in a polycrystalline silicon layer covered with an o...	03/06/2012
8129246	Advanced CMOS using super steep retrograde wells The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS tran...	03/06/2012
8129089	Use of blended solvents in defectivity prevention The present invention provides a blended solvent for solubilizing an ultraviolet photoresist. The blended solvent comprises a mixture of from about 5 vol % to about 95 vol % of a first solvent, wherein the first solvent comprises a cyclic ester. A balance of the mix...	03/06/2012
8126681	Semiconductor outlier identification using serially-combined data transform processing methodologies A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain electrical test data including at least one test parameter, applying at least a first data transform processin...	02/28/2012
8125054	Semiconductor device having enhanced scribe and method for fabrication In a semiconductor device for use in a wafer level chip scale package (WLCSP) and a method for fabrication, an inner scribe seal is formed around a functional circuit area that does not extend all the way into the corners of the rectangular die, and an outer scribe ...	02/28/2012
8125053	Embedded scribe lane crack arrest structure for improved IC package reliability of plastic flip chip devices A system, method, and apparatus for suppressing cracks in the wafer dicing process. A wafer includes a plurality of die attached to a frame and mounting tape, with the die separated by a plurality of scribe lanes. An existing die seal generally protects the boundary...	02/28/2012
8125035	CMOS fabrication process Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverse...	02/28/2012
8125030	High voltage SCRMOS in BiCMOS process technologies An integrated circuit containing an SCRMOS transistor. The SCRMOS transistor has one drain structure with a centralized drain diffused region and distributed SCR terminals, and a second drain structure with distributed drain diffused regions and SCR terminals. An MO...	02/28/2012
8124511	Method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder One aspect provides a method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder. In one aspect, this improvement is achieved by forming gate electrodes over a semiconductor substrate, amorphizing the semiconductor substrate t...	02/28/2012
8124486	Method to enhance channel stress in CMOS processes The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interf...	02/28/2012
8124482	MOS transistor with gate trench adjacent to drain extension field insulation An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transi...	02/28/2012
8120108	High voltage SCRMOS in BiCMOS process technologies An integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal. The RESURF region is the same conductivity type as the drift region and is more heavily doped than the drift region. An SCRMOS transistor with a RESURF r...	02/21/2012
8114784	Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD ...	02/14/2012
8114727	Disposable spacer integration with stress memorization technique and silicon-germanium An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (	02/14/2012
8112168	Process and method for a decoupled multi-parameter run-to-run controller A manufacturing process including a controller method to generate a tool setting which includes a tool offset and a device offset. The controller method uses a device parameter measurement to update the tool offset and device offset. A tool weight and a device weigh...	02/07/2012
8101476	Stress memorization dielectric optimized for NMOS and PMOS A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not...	01/24/2012
8084787	PMD liner nitride films and fabrication methods for improved NMOS performance Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in ail or a portion of the NMOS transistor to improve carrier mobility. The nitride l...	12/27/2011
8084312	Nitrogen based implants for defect reduction in strained silicon A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating charact...	12/27/2011
8058122	Formation of metal gate electrode using rare earth alloy incorporated into mid gap metal Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the ga...	11/15/2011
8056029	Merging sub-resolution assist features of a photolithographic mask Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second sub-resolution assist feature. A merge bar width of a merge bar is est...	11/08/2011
8053256	Variable thickness single mask etch process The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semicon...	11/08/2011
8053252	Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The ...	11/08/2011
8049254	Semiconductor device with gate-undercutting recessed region A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral openin...	11/01/2011
8048750	Method to enhance channel stress in CMOS processes The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interf...	11/01/2011
8043921	Nitride removal while protecting semiconductor surfaces for forming shallow junctions A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sid...	10/25/2011
8026507	Two terminal quantum device using MOS capacitor structure A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot ...	09/27/2011
8026135	Formation of shallow junctions by diffusion from a dielectric doped by cluster or molecular ion beams A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm−2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric laye...	09/27/2011
8021990	Gate structure and method A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition. ...	09/20/2011
8017493	Method of planarizing a semiconductor device A process of forming a semiconductor process fabricated device which contains a trench, hole or gap filled with a conformally deposited material is disclosed. A sacrificial planarizing layer is formed on the fill material, and the device is planarized using a select...	09/13/2011
8012879	Etching method using an at least semi-solid media An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove meta...	09/06/2011
8012844	Method of manufacturing an integrated circuit A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing an electrically insulating layer on the resistor layer, removing the electrically insulating layer...	09/06/2011
7994009	Low cost transistors using gate orientation and optimized implants An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the...	08/09/2011

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Attorney: Garner; Jacqueline J.