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| Number | Title | Issue Date |
| 7715794 | Bluetooth fast connection mode for wireless peripheral device A wireless interface device services communications between a wirelessly enabled host and at least one user input device. The wireless interface device includes a wireless interface unit, a processing unit, an input/output unit, and a power management unit. The wire... | 05/11/2010 |
| 7506148 | Wireless human interface device host interface supporting both BIOS and OS interface operations A host-side wireless interface services communications between a wireless user input device and a serviced host. The host-side wireless interface includes a wireless network interface, a host interface, and may include additional components. The wireless network int... | 03/17/2009 |
| 7406344 | Wireless network card with antenna selection option A wireless network card includes an adaptable antenna connection structure that includes connections for one or more internal antennas and for one or more Radio Frequency (RF) connectors that may be coupled to one or more external antennas. A Printed Circuit Board (... | 07/29/2008 |
| 7260357 | Bluetooth fast connection mode for wireless peripheral device A wireless interface device services communications between a wirelessly enabled host and at least one user input device. The wireless interface device includes a wireless interface unit, a processing unit, an input/output unit, and a power management unit. The wire... | 08/21/2007 |
| 7257154 | Multiple high-speed bit stream interface circuit A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB) or the communication ASIC to another communication ASIC. The high-speed bit strea... | 08/14/2007 |
| 7218911 | Communication device with a self-calibrating sleep timer The present invention provides for a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a dual mode timer (70) that extends battery life. A controller (50) schedules the... | 05/15/2007 |
| 7212516 | Network spanning heterogeneous call center and method of operation A network spanning heterogeneous call center system and method of operation is disclosed. A particular illustrative system is for use with a circuit-switched private branch exchange and a packet-switched private branch exchange. This system includes a circuit-switch... | 05/01/2007 |
| 7165171 | Wireless human interface device host interface supporting both BIOS and OS interface operations A host-side wireless interface services communications between a wireless user input device and a serviced host. The host-side wireless interface includes a wireless network interface, a host interface, and may include additional components. The wireless network int... | 01/16/2007 |
| 7151745 | Scalable synchronous packet transmit scheduler A baseband controller system creates and maintains a schedule of synchronized events and reviews the schedule as a part of determining whether to initiate a transmission of a non-synchronous event. One aspect is to avoid a possibility of collision between synchroniz... | 12/19/2006 |
| 7129755 | High-fanin static multiplexer An improved high-fanin multiplexer that is highly-scalable, fast and area-efficient. In one embodiment of the present invention, multiple logic “legs” are attached to a common output line. Each leg comprises one pMOS pull-up transistor and one nMOS pull-down tra... | 10/31/2006 |
| 7131020 | Distributed copies of configuration information using token ring A system for synchronizing configuration information in a plurality of data processing devices using a common system interconnect bus. The present invention provides a method and apparatus for enforcing automatic updates to the configuration registers in various age... | 10/31/2006 |
| 7130670 | Wireless network card with antenna selection option A wireless network card includes an adaptable antenna connection structure that includes connections for one or more internal antennas and for one or more Radio Frequency (RF) connectors that may be coupled to one or more external antennas. A Printed Circuit Board (... | 10/31/2006 |
| 7129574 | Multi-power ring chip scale package for system level integration A scalable multi-power integrated circuit package for integrated circuits having spaced apart first, second and third pluralities of respective spaced apart chip power bonding pads connected to-corresponding first, second, and third chip power supply nets, the chip ... | 10/31/2006 |
| 7129589 | Use of an internal on-chip inductor for electrostatic discharge protection of circuits which use bond wire inductance as their load A circuit includes a plurality of circuit components formed on a semi conductive substrate die and a bond wire. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coupled to the at least on... | 10/31/2006 |
| 7129784 | Multilevel power amplifier architecture using multi-tap transformer A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is described. By providing a multi-tap transformer for coupling a plurality of power amplifiers to a shared output... | 10/31/2006 |
| 7113540 | Fast computation of multi-input-multi-output decision feedback equalizer coefficients Multi-Input-Multi-Output (MIMO) Optimal Decision Feedback Equalizer (DFE) coefficients are determined from a channel estimate h by casting the MIMO DFE coefficient problem as a standard recursive least squares (RLS) problem and solving the RLS problem. In one embodi... | 09/26/2006 |
| 7103121 | Frequency diverse single carrier modulation for robust communication over in-premises wiring The present invention provides a frequency-diverse single-carrier modulation scheme that extends the usable SNR range of severely distorted channels. This scheme is advantageous for applications in which when the SNR is low and the transmitted spectrum contains unus... | 09/05/2006 |
| 7099416 | Single ended termination of clock for dual link DVI receiver A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock sign... | 08/29/2006 |
| 7096305 | Peripheral bus switch having virtual peripheral bus and configurable host bridge A peripheral bus switch includes a virtual peripheral bus, a plurality of bridges, and a configurable host bridge. A first bridge operably couples on a first side to the virtual peripheral bus and supports connection on a second side to a peripheral bus fabric. A se... | 08/22/2006 |
| 7092466 | System and method for recovering and deserializing a high data rate bit stream A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bi... | 08/15/2006 |
| 7092727 | Apparatus and method for supporting differentiated packet data services within a wireless network A system and method manages Radio Access Network (RAN) resources to service packet data transmissions at Service Quality Levels (SQL) commensurate with packet data network SQLs. A Packet Data Serving Node (PDSN) receives a data packet from a coupled packet data netw... | 08/15/2006 |
| 7075913 | Hybrid data rate control in CDMA cellular wireless systems A method for servicing high-speed data communications in a cellular wireless communication system includes the wireless transmission of data at a higher data rate than is supportable considering constraints of the prior art. The cellular wireless communication syste... | 07/11/2006 |
| 7072307 | Hybrid ARQ schemes with soft combining in variable rate packet data applications A system and method for transmitting high speed data on fixed rate and for variable rate channels. The system and method provides the flexibility of adjusting the data rate, the coding rate, and the nature of individual retransmissions. Further, the system and metho... | 07/04/2006 |
| 7068609 | Method and apparatus for performing wire speed auto-negotiation Auto-negotiation with a communication partner includes downgrading a set of advertised communications capabilities, e.g., IEEE 802.3 capabilities, when a link with the communication partners fails to support an advertised communications capability, e.g., wire-speed.... | 06/27/2006 |
| 7068728 | Carrierless backwards compatible data neworking transmitter, receiver, and signal format New version packet data devices support a backwards-compatible signal format. New version devices operate within a first frequency band while old version devices operate within a second frequency band. The first frequency band differs from but overlaps with the seco... | 06/27/2006 |
| 7065693 | Implementation of test patterns in automated test equipment An improved automated testing system that decreases the number of test signals that must be stored in the tester pattern memory for a timed test pattern. In the present invention, a timed test pattern is controlled by a timing generator operable to change the timing... | 06/20/2006 |
| 7046773 | System and method for preventing telephone line blocking by a modem A modem includes a Digital Access Arrangement (DAA) Circuit and modem software that is executed by a processor. When the DAA Circuit detects that the modem software is nonfunctional, it enters an on-hook state to prevent blocking of a coupled telephone line. A nonfu... | 05/16/2006 |
| 7031676 | Radio frequency transmitter having translational loop phase equalization A Radio Frequency RF transmitter includes a translational loop architecture that supports non-constant envelope modulation types and includes by adjusting the envelope of the translational loop at the translational loop output. The RF transmitter includes a phase eq... | 04/18/2006 |
| 7031401 | Digital to analog converter with time dithering to remove audio tones A Digital-to-Analog-Converter (DAC) includes an interpolation filter, a modulator, and a time dither clock reduction circuit. The interpolation filter receives the digital data and interpolates and filters the digital data to produce an interpolated and filtered dig... | 04/18/2006 |
| 7027539 | Pipeline architecture for multi-slot wireless link processing A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a positive integer greater than one. The wireless communication device includes an RF front end, a baseband ... | 04/11/2006 |
| 7027504 | Fast computation of decision feedback equalizer coefficients Optimal Decision Feedback Equalizer (DFE) coefficients are determined from a channel estimate h by casting the DFE coefficient problem as a standard recursive least squares (RLS) problem, e.g., the Kalman gain solution to the RLS problem. A fast recursive method, e.... | 04/11/2006 |
| 7002238 | Use of a down-bond as a controlled inductor in integrated circuit applications A Radio Frequency (RF) device includes a semi conductive die and a package in which the semi conductive die mounts. The semi conductive die includes a first portion of an RF circuit and a plurality of die pads formed thereon. The package includes a heat slug upon wh... | 02/21/2006 |
| 6998921 | Method for avoiding avalanche breakdown caused by a lateral parasitic bipolar transistor in an MOS process A power amplifier includes a transconductance stage, a cascode stage, and a connector. The transconductance stage is operable to receive an input voltage signal and to produce an output current signal. The cascode stage communicatively couples to the transconductanc... | 02/14/2006 |
| 6995616 | Power amplifier having cascode architecture with separately controlled MOS transistor and parasitic bipolar transistor A power amplifier includes a transconductance stage, a cascode stage, and may include a signal level detection and bias determination module. The transconductance stage is operable to receive an input voltage signal and to produce an output current signal. The casco... | 02/07/2006 |
| 6985755 | Reduced power consumption wireless interface device A wireless interface device services communications between a wirelessly enabled host and at least one user input device. The wireless interface device includes a wireless interface unit, a processing unit, an input/output unit, and a power management unit. The wire... | 01/10/2006 |
| 6985705 | Radio frequency control for communication systems The present invention provides for a system and method for improvement of radio transmitter and receiver frequency accuracy for a local radio communication unit that communicates digital data with a remote communication unit. In the local unit the received radio sig... | 01/10/2006 |
| 6981074 | Descriptor-based load balancing A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plu... | 12/27/2005 |
| 6972629 | Modulation dependent biasing for efficient and high-linearity power amplifiers A power amplifier includes a transconductance stage and a modulation detection and bias determination module, and may include a cascode stage. The modulation detection and bias determination module operably couples to the transconductance stage and to the cascode st... | 12/06/2005 |
| 6970689 | Programmable mixer for reducing local oscillator feedthrough and radio applications thereof A state of a programmable mixer is set during a calibration phase to minimize local oscillator feedthrough. During a calibration phase, inputs to the programmable mixer are set to zero, or to a known state and the local oscillator is set to a calibration frequency. ... | 11/29/2005 |
| 6956835 | Multi-carrier arrangement for high speed data The system and method of the present invention uses a plurality of carriers by assigning user terminals to the plurality of carriers so that a minimum grade of service is met and so that throughput is maximized. Each serviced user terminal reports the channel qualit... | 10/18/2005 |
