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| Number | Title | Issue Date |
| 7945258 | Wireless device operable to manipulate high-speed shared control channel (HSSCCH) quality control through channel quality indication report manipulation A method to adapt channel quality indicator (CQI) reports from user equipment (UE) is provided. This involves first determining the presence of a high-speed shared control channel (HS-SCCH) signal. An estimated signal to noise ratio (SNR) is also determined. Next an... | 05/17/2011 |
| 7945216 | Single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing A single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing is provided. This processing may be divided between various processing modules. This single chip includes a processing module having an ARM microprocessor and a di... | 05/17/2011 |
| 7944907 | Temporal alignment of codec data with wireless local area network RF slots A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other WLAN device. The WLAN transceiving integrated circuit includes a WLAN interface, an input buffer, a transcoder, and a processor. The ... | 05/17/2011 |
| 7944659 | ESD protection circuit for high speed signaling including a switch An ESD protection circuit for a switch coupled to high-speed signaling pins of an integrated circuit includes a first string of clamping elements and a second string of clamping elements. The first string of clamping elements has a collective capacitance less than t... | 05/17/2011 |
| 7944403 | RF reception system and integrated circuit with programmable impedance matching network and methods for use therewith An integrated circuit includes an on-chip antenna interface, coupled to an off-chip antenna interface having at least one off-chip impedance matching component, that forms a programmable impedance matching network with the at least one off-chip impedance matching co... | 05/17/2011 |
| 7944398 | Integrated circuit having a low efficiency antenna An integrated circuit (IC) includes an RF transceiver, a die, a package substrate, an antenna element, and a transmission line circuit. The die supports the RF transceiver and the package substrate supports the die. The antenna element has a length less than approxi... | 05/17/2011 |
| 7944380 | Wireless local area network device supporting enhanced call functions A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other wireless device and includes a WLAN interface, a transcoder, and a switch box. The WLAN interface wirelessly communicates with at lea... | 05/17/2011 |
| 7944376 | Technique for improving modulation performance of translational loop RF transmitters A transmit signal generated by the baseband processor in a translational loop type RF transmitter is “pre-distorted” so as to counter act magnitude distortion and group delay variation imposed by a narrow PLL signal filter. The pre-distortion occurs in two steps... | 05/17/2011 |
| 7535972 | Programmable transmitter A programmable transmitter generates a frame in a frame format according to one of a plurality of operating modes using a frame structure table storing a respective frame format for each of the operating modes. The transmitter includes a frame structure engine that ... | 05/19/2009 |
| 7490187 | Hypertransport/SPI-4 interface supporting configurable deskewing A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a physical interface, a plurality of data line amplifiers, a clock line amplifier, a plurality of data line deskew/... | 02/10/2009 |
| 7489741 | System and method to perform DC compensation on a radio frequency burst in a cellular wireless network A method to perform DC compensation on a Radio Frequency (RF) burst transmitted between a servicing base station and a wireless terminal in a cellular wireless communication system that first receives the RF burst modulated according to either a first or second modu... | 02/10/2009 |
| 7463310 | BTSC pilot signal lock An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit is described. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate... | 12/09/2008 |
| 7464310 | Programmable state machine of an integrated circuit A programmable state machine of an application specific integrated circuit (ASIC) is programmed by enabling the scan mode of the integrated circuit. The process of programming the state machine continues by loading, through at least one scan chain to which the state... | 12/09/2008 |
| 7463600 | Frame structure for variable rate wireless channels transmitting high speed data A frame structure that is optimized for providing variable high data rates. Superframes, each comprised of a predetermined number of frames, carry data communications at one or more variable data rates. Each data customer is allotted one or more frames or portions o... | 12/09/2008 |
| 7464317 | Decoding LDPC (low density parity check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. Decoding of LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain addi... | 12/09/2008 |
| 7463176 | DAC module and applications thereof A digital to analog conversion (DAC) module includes a digital to analog converter, a sample and hold circuit, and a switch module. The digital to analog converter is coupled to convert a digital signal into an analog signal. The sample and hold circuit is coupled t... | 12/09/2008 |
| 7463871 | Processing received digital data signals based on a received digital data format An integrated circuit radio receiver includes radio frequency (“RF”) front end circuitry for receiving and transmitting digital data received through a wireless interface. A baseband processor is operable to process the digital data received through the wireless... | 12/09/2008 |
| 7460608 | Parallel concatenated code with soft-in soft-out interactive turbo decoder A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provide... | 12/02/2008 |
| 7460594 | Fast computation of linear equalizer coefficients from channel estimate Computing optimal Linear Equalizer (LE) coefficients gopt from a channel estimate h. A channel impulse response h is first estimated based upon either a known training sequence or an unknown sequence. The channel estimate is formulated as a convolution ma... | 12/02/2008 |
| 7460515 | Access control by call type A packet data service node (PDSN) is formed to establish a connection with a plurality of mobile terminals by way of one or more packet control function cards or devices. A packet control function (PCF) card or device is formed to provide an interface between the pa... | 12/02/2008 |
| 7459969 | Transmitter power amplifier working at different power supplies A method to reduce transmitted output power and the battery consumption is provided. This involves first determining the required output level. The amplitude of the input signal provided to a PA driver may be based on the required output power level. This amplitude ... | 12/02/2008 |
| 7461197 | Disk formatter and methods for use therewith A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address... | 12/02/2008 |
| 7457352 | Cancellation of interference in a communication system with application to S-CDMA Cancellation of interference in a communication system with application to S-CDMA. A relatively straight-forward implemented and computationally efficient approach of selecting a predetermined number of unused codes is used to perform weighted linear combination sel... | 11/25/2008 |
| 7457379 | Adaptive multi-step combined DC offset compensation for EDGE 8-PSK A method to perform DC compensation on a Radio Frequency (RF) burst transmitted between a servicing base station and a wireless terminal in a cellular wireless communication system that first receives the RF burst modulated according to either a first or second modu... | 11/25/2008 |
| 7457380 | Low noise circuit and applications thereof A low noise circuit includes a clocked circuit and an impedance trap circuit. The clocked circuit includes a clock input, an input, an output, a power supply connection, and a power return connection. The clock input is operably coupled to receive a clock signal. Th... | 11/25/2008 |
| 7456761 | Interspersed training among encoded blocks of data within a data frame A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver sys... | 11/25/2008 |
| 7457351 | Cancellation of interference in a communication system with application to S-CDMA Cancellation of interference in a communication system with application to S-CDMA. A relatively straight-forward implemented and computationally efficient approach of selecting a predetermined number of unused codes is used to perform weighted linear combination sel... | 11/25/2008 |
| 7453839 | Wireless local area network channel resource management A wired Local Area Network (wired LAN) and a plurality of Wireless Access Points (WAPs) coupled to a wired network infrastructure of the wired LAN service wireless packetized communications for a plurality of Wireless Local Area Network (WLAN) clients. A multi-layer... | 11/18/2008 |
| 7454189 | Calibration of received signal strength indication Calibration of received signal strength indication (RSSI) within a radio frequency integrated circuit (RFIC) begins by concurrently enables a transmitter portion and receiver portion. With both the transmitter and receiver enabled, the RFIC provides a zero input to ... | 11/18/2008 |
| 7452160 | Waste water electrical power generating system An environmental protective electrical power generating system is formed by a penstock connected at its opposite ends to a large sewer for conveying waste water from feeder pipelines to a sanitary treatment station. Sewer waste water is propelled through the sewer l... | 11/18/2008 |
| 7450676 | Synchronization of data links in a multiple link receiver A dual link receiver terminates, recovers, channel aligns, and link aligns a plurality of primary link channels and a plurality of secondary link channels. The plurality of primary link channels and the plurality of secondary link channels are each received, bit rec... | 11/11/2008 |
| 7450518 | Sparse channel dual-error tracking adaptive filter/equalizer An adaptive filter has a plurality of filter coefficients and a filter coefficients processing unit trains of the adaptive filter. The filter coefficients processing unit is operable to iterate to alter the plurality of filter coefficients of the communication syste... | 11/11/2008 |
| 7449964 | System and method for tuning output drivers using voltage controlled oscillator capacitor settings The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This o... | 11/11/2008 |
| 7449365 | Wafer-level flipchip package with IC circuit isolation Forming a wafer level chip scale flip chip package includes determining isolation requirements of an integrated circuit formed in a semi conductive substrate from package signal connections of the wafer level chip scale flip chip package. Operation may further inclu... | 11/11/2008 |
| 7451386 | LDPC (Low Density Parity Check) coded modulation hybrid decoding LDPC (Low Density Parity Check) coded modulation hybrid decoding. A novel approach is presented wherein a combination of bit decoding and symbol level decoding (e.g., hybrid decoding) is performed for LDPC coded signals. Check node updating and symbol node updating ... | 11/11/2008 |
| 7450635 | Single antenna interference cancellation within a wireless terminal The present invention provides a multi-branch equalizer processing module operable to cancel interference associated with received radio frequency (RF) burst(s). This multi-branch equalizer processing module includes both a first equalizer processing branch and a se... | 11/11/2008 |
| 7447981 | System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave. A novel approach is presented that combines different coding types within a communication system to perform various ty... | 11/04/2008 |
| 7447985 | Efficient design to implement min**/min**- or max**/max**- functions in LDPC (low density parity check) decoders Efficient design to implement min**/min**− or max**/max**− functions in LDPC (Low Density Parity Check) decoders. When compared to prior art approaches, the novel and efficient implementation presented herein allows for the use of substantially less hardware and... | 11/04/2008 |
| 7443930 | Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a... | 10/28/2008 |
| 7443867 | Method for performing network services The methods of the present invention enable wireless gateway nodes to support mobile node services, such as content based billing, when a data treatment server is present in the system. Using one of a defined Content Flow Label (CFL), an Application Program Interfac... | 10/28/2008 |
