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| Number | Title | Issue Date |
| 7262628 | Digital calibration with lossless current sensing in a multiphase switched power converter Disclosed is a multi-phase power regulator that accurately senses current at a load in a lossless manner and adjusts the power supplied to the load based on the sensed current. Also disclosed is a method of calibrating a multiphase voltage regulator by applying a kn... | 08/28/2007 |
| 7239116 | Fine resolution pulse width modulation pulse generator for use in a multiphase pulse width modulated voltage regulator Disclosed is a fine resolution pulse width generator for use in a multiphase pulse width modulated voltage regulator. The fine pulse width is generated by first generating a pulse with a coarse pulse width and one or more delayed replicas thereof. Then, digitally co... | 07/03/2007 |
| 7006543 | System and circuit for a multi-channel optoelectronic device driver Disclosed is a system and circuit for a multi-channel optoelectronic device driver. The system and circuit include a differential buffer amplifier, an output driver amplifier, a dedicated voltage regulator, a load compensation circuit, a wave shaping circuit and a l... | 02/28/2006 |
| 7007176 | System and method for highly phased power regulation using adaptive compensation control A highly phased power regulation (converter) system having an improved control feature is provided. A controller, such as a digital signal processor or microprocessor, receives digital information from a plurality of power conversion blocks and transmits control com... | 02/28/2006 |
| 7002249 | Microelectronic component with reduced parasitic inductance and method of fabricating A semiconductor device package is disclosed which includes inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device. In one embodiment, t... | 02/21/2006 |
| 6960031 | Apparatus and method of packaging two dimensional photonic array devices An optical coupler for forming an optical connection between one or more two dimensional photonic array devices and an optical fiber and for forming an electrical connection between the two dimensional photonic array devices and a substrate, a system including the o... | 11/01/2005 |
| 6937685 | Apparatus and method for counting high-speed early/late pulses from a high speed phase detector using a pulse accumulator The method and device according to the present invention provides a control system, method and apparatus for synchronizing a reference signal to high frequency data signals. Pulses are accumulated before reaching the integrator. Pulse accumulation is provided in a D... | 08/30/2005 |
| 6847197 | System and method for detection of zero current condition A method for converting power includes charging an inductor by coupling the inductor to a voltage source for a predetermined amount of time. Thereafter, the inductor is discharged by coupling the inductor to a ground until the current flowing through the inductor eq... | 01/25/2005 |
| 3961250 | Logic network test system with simulator oriented fault test generator Disclosed is a technique for testing highly complex, functional logic where long sequences of test patterns are needed. A logic network to be tested comprises a large number of logic blocks. The inputs to several of these logic blocks are also the primary... | 06/01/1976 |
| 3949228 | Method for controlling an electron beam A square-shaped electron beam is stepped from one predetermined position to another in a line-by-line scan to form a desired pattern on each chip of a semiconductor wafer to which the beam is applied. At each of the predetermined positions, the beam is on... | 04/06/1976 |
| 3949385 | D.C. Stable semiconductor memory cell Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-cou... | 04/06/1976 |
| 3949383 | D. C. Stable semiconductor memory cell Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross cou... | 04/06/1976 |
