Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 6426953 | Method of operating an internal high speed ATM bus inside a switching core The ATM bus (100) is composed of a clock signal, CLK, a synchronization signal, -SYNC, a data bus, S(0-31), and an adapter identification bus, SID(0-3). It is a synchronous bus running at any clock rates. The clock signal is generated by the backplane (20... | 07/30/2002 |
| 6373818 | Method and apparatus for adapting window based data link to rate base link for high speed flow control A system and method for converting a window based data link flow control to a rate based flow control. In addition to the conventional data link control window, a second window is established under control of an adaptive committed information rate (ACIR).... | 04/16/2002 |
| 6321312 | System and method for controlling peripheral device memory access in a data processing system A cache based processing system is provided with a loop detection circuit for detecting the entry into and termination of program loops and for enabling peripheral device access to the main memory after completion of the first pass through the loop and te... | 11/20/2001 |
| 6047336 | Speculative direct memory access transfer between slave devices and memory A DMA Controller, in response to a data transfer request from a slave device, initiates a memory transfer cycle and informs the slave device when the data transfer has completed. In order to avoid dead clock cycles on internal bus(es), the DMA Controller ... | 04/04/2000 |
| 5878382 | Method and apparatus for timing and monitoring inactivity periods A method and apparatus for detecting the absence of an activity or event during a time period D divides the time period D into N equal time sub-periods. A register is reset upon the occurrence of an event or activity. The register is incremented at the en... | 03/02/1999 |
| 5051892 | Full duplex conversation between transaction programs A method for the full duplex exchange of data via a conversation between a pair of transaction programs over a network in which any transaction program which requests a confirmation of previously sent data inhibits the further transmission of data until a... | 09/24/1991 |
| 5048055 | Multi-data rate selectable equalizer An equalizer circuit suitable for selectively equalizing a transmission media operating at one of a number of different data rates has a number of equalizers, one for each data rate, connected in parallel to the media and a selectively operable means for ... | 09/10/1991 |
| 5036514 | Apparatus and method for isolating and predicting errors in a local area network A method for correcting error weights in a communication system in which at least one error condition can result from more than one cause. Stations on the system send error reports to an error monitor station which maintains a count of the number of stati... | 07/30/1991 |
| 5001758 | Voice coding process and device for implementing said process The voice signal is analyzed to derive therefrom a low frequency base band signal, linear prediction coefficients and high frequency (HF) descriptors. Said HF descriptors include HF energy indications as well as indications relative to the phase shift bet... | 03/19/1991 |
| 4975914 | Non-disruptive session recovery A method of operating a communication system which includes a number of host systems each communicating via sessions with other devices over different connections and in which the sessions assigned to a failed connection are suspended for a first and seco... | 12/04/1990 |
| 4941152 | Signal coding process and system for implementing said process A signal coding process more particularly suitable for coding a voice signal. At least a portion of the frequency bandwidth of said voice signal is split into several subbands, the content of which is then requantized using a dynamic allocation of requant... | 07/10/1990 |
| 4907277 | Method of reconstructing lost data in a digital voice transmission system and transmission system using said method A method of reconstructing, at the receiving end, digital data defining an encoded voice signal segment lost in transmission between the transmitter and the receiver in a transmission system wherein a low-frequency signal such as a residual baseband signa... | 03/06/1990 |
| 4902258 | Robotic assembly system A robotic assembly system for the automatic assembly of a complex article such as a CRT display unit has a number of workstations positioned along an open conveyor system at each of which as assembly operation is performed by a conventional stand-alone ro... | 02/20/1990 |
| 4876644 | Parallel pipelined processor A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines ... | 10/24/1989 |
| 4845752 | Multi-signal processor synchronized system A multiprocessor system includes a plurality of signal processors and a common unit processor. Each of the signal processors is connected to a different source of signals such as voice signals and performs one or more signal processing functions relative ... | 07/04/1989 |
| 4843606 | Local area communication system for integrated services based on a token-ring transmission medium In a local area communication system comprising token rings (11) with synchronous bandwidth managers SBM (15) for issuing priority tokens for quasi-synchronous frames at regular intervals, the rings are interconnected by a time division muliplex PBX unit ... | 06/27/1989 |
| 4823339 | Method and device for protecting modems against echoes The device for providing protection against echoes includes a level memory (33) for storing a value Gs and a comparator (34) for comparing the level Gx provided by an AGC device (31) upon receipt of a message with a value Gs stored in the level memory (33... | 04/18/1989 |
| 4794594 | Method and system of routing data blocks in data communication networks The invention relates to a method of routing data blocks in a data communication network comprising a plurality of nodes through which the data blocks are routed. A node identifier and a port identifier are assigned to each node and to each port in the no... | 12/27/1988 |
| 4790015 | Multirate digital transmission method and device for implementing said method This coder dispatches the bits resulting from the coding operation of a speech signal into a format for transmission at a rate chosen from a plurality of predetermined transmission rates. More specifically, the contents of at least part of the speech sign... | 12/06/1988 |
| 4764955 | Process for determining an echo path flat delay and echo canceler using said process In a voice transmission network having an echo canceler including a flat delay line in series with an adaptive digital filter, a process is provided for adjusting the flat delay line length, thus enabling limiting the filter length to minimal value. The m... | 08/16/1988 |
| 4763321 | Dynamic bandwidth allocation mechanism between circuit slots and packet bit stream in a communication network System for dynamically allocating circuit slots in frames which are used for exchanging bits between users connected to nodes of a communication network linked by means of medium links having transmit and receive interfaces, the frames are delimited by fl... | 08/09/1988 |
| 4761781 | Adaptative packet/circuit switched transportation method and system Method and system for configuring a succession of complex frames to be used for exchanging synchronous circuit switched bits and asynchronous packet switched bits between nodes connected through medium links working at any bit rates in a teleprocessing ne... | 08/02/1988 |
| 4760573 | Multiplex interface for a communication controller A multiplex interface for interconnecting the line scanning means (1) of a communication controller to user lines via transmit and receive synchronous multiplex links. Both data and control bits are exchanged in synchronous frames wherein at least two slo... | 07/26/1988 |
| 4752872 | Arbitration device for latching only the highest priority request when the common resource is busy An arbitration device for enabling a common resource to be shared by a plurality of processors, all connected by a common bus and each processor having a certain access priority. When more than one processor requests access to the resource, the highest pr... | 06/21/1988 |
| 4751730 | Process and system for improving echo cancellation within a transmission network This process enables cancelling residual echo signals in a transmission system wherein echo signals are partially cancelled through use of a filter generating an echo replica, and substracting said replica from the signal in the echo path. The process inv... | 06/14/1988 |
| 4751703 | Method for storing the control code of a processor allowing effective code modification and addressing circuit therefor A method for storing the control code of a processor in a read only memory ROM (5) and in a read/write memory RAM (7) comprising a code area and a patch area. It consists in virtually dividing the control code in blocks of n instructions, storing the firs... | 06/14/1988 |
| 4751698 | Serial link adapter for a communication controller Serial link adapter to be used in a communication controller comprising data handling means (DHM), said adapter allowing the communication controller to be attached to a multiplex serial link carrying data and non coded information bits in dedicated slots... | 06/14/1988 |
| 4751510 | Method and system for controlling a network of modems A DTE can control the modems attached thereto by transmitting command messages over the data path and analyzing report messages supplied by the modems in return. Each command message is identified by a specific header. A command message intended for a rem... | 06/14/1988 |
| 4748587 | Device for improving detection of unoperational states in non-attended driven processor Device for detecting the unoperational states of an interrupt driven processor executing instructions on n priority levels, n-1 being the lowest priority level and 0 the highest priority level. It comprises means (18) for dispatching the unoperational sta... | 05/31/1988 |
| 4734676 | Method and device for detecting a particular bit pattern in a serial train of bits Memory 60 contains a decision table which is a replica of the particular N-bit pattern to be detected. When a bit is received over line 12, a table lookup operation is performed to determine whether the entry at the address indicated by address counter 34... | 03/29/1988 |
| 4731784 | Communication system comprising overlayed multiple-access transmission networks In a communication system providing multiple access to transmission facilities for a plurality of stations (17, 21), two separate networks (11, 13) are provided: One is a token ring (11) on which access tokens and data are transmitted, the other is a high... | 03/15/1988 |
| 4731829 | Circuit for detecting current variations The circuit of the present invention detects variations of a current IL flowing in a telephone line LL. A low-value resistor r is connected in series with line LL. A constant voltage generator is connected across this resistor. The current Is a... | 03/15/1988 |
| 4703364 | Processor synchronous image scanner controlling method The invention directly controls the start of application of clock pulses to a shift register of an image sensor unit in synchronism with read signals supplied from a processor unit, to transfer video data of successive scan lines of an image. Transfer tim... | 10/27/1987 |
| 4695997 | Device for performing wrap tests on a multiplex link in a data communication system In a data communication system, a device for performing a wrap test on at least one line without affecting the other lines that transmit and receive data over at least one multiplex link (4) within time slots allocated to a given line within a given frame... | 09/22/1987 |
| 4677648 | Digital phase locked loop synchronizer A phase locked loop (PLL) arrangement comprising a local crystal oscillator (23) and a tapped delay chain (15) of analog delay elements (17). Connected to the delay chain taps are a flash register (25) consisting of latches which store the tap signal valu... | 06/30/1987 |
| 4677671 | Method and device for coding a voice signal A voice signal coding method is provided for processing the residual base-band signal provided by a Voice Excited Predictive (VEPC) Coder. The residual signal is split over several sub-bands and the contents of each sub-band is dually coded by using a pro... | 06/30/1987 |
| 4674103 | Method and arrangement for detecting the presence of a training signal in a modem receiver For rapidly detecting a periodic training signal in a modem receiver, delay line storage (21) is provided for a signal section which is equal to one training signal period (q.multidot.M samples) plus an additional adjacent window (q.multidot.W samples). T... | 06/16/1987 |
| 4672669 | Voice activity detection process and means for implementing said process Speech signal presence is detected in a VAD (Voice Activity Detector) in two steps: (1) Signal energy above a threshold decides presence, below threshold decides ambiguity; (2) ambiguity is resolved by testing the rate of change of spectral parameters.... | 06/09/1987 |
| 4667182 | Stylus or pen with tactile response to user A stylus for interactive use with a graphics input tablet provides a user with a tactile response whenever the stylus tip (5) passes through the in-presence boundary of the tablet. The boundary defines the limit of the distance of the stylus above the tab... | 05/19/1987 |
| 4656643 | Line interface circuit A line interface circuit for connecting the transmit and receive ports of a transmitter to transmit lines (LX) and receive lines (LR), respectively. The interface circuit includes a transistorized differential amplifier provided with two load circuits com... | 04/07/1987 |
