Bizarre Patents
Pneumatic Shoe Lacing Apparatus
This invention provides a pneumatic shoe lacing apparatus for the pneumatic lacing of shoe.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8176443 | Layout of printable assist features to aid transistor control Exemplary embodiments provide a method for laying out an IC design and the IC design layout. The IC design layout can include one or more gate features placed on an active region including a first pitch (p1) between any two adjacent gate features. Additionall... | 05/08/2012 |
| 8176241 | System and method for optimizing DRAM refreshes in a multi-channel memory controller In accordance with the teachings of the present invention, a system and method for optimizing DRAM refreshes in a multi-channel memory controller are provided. In a particular embodiment, the method includes receiving, at a router in a light modulation system, a sig... | 05/08/2012 |
| 8174545 | Mitigation of temporal PWM artifacts A system and method for reducing pulse width modulation contouring artifacts. Each input intensity value is translated to at least one non-binary bit pattern for display. Many of the input intensity values are translated to at least two alternate non-binary bit patt... | 05/08/2012 |
| 8174077 | High-voltage variable breakdown voltage (BV) diode for electrostatic discharge (ESD) applications Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is ... | 05/08/2012 |
| 8174058 | Integrated circuits with split gate and common gate FinFET transistors An integrated circuit includes common gate FinFET and split gate FinFET devices formed from different height fins at a semiconductor surface of a substrate. A patterned layer of gate electrode material formed over sides and unconnected over the tops of the taller fi... | 05/08/2012 |
| 8173544 | Integrated circuit having interleaved gridded features, mask set and method for printing A method (300) for fabricating an integrated circuit includes the step of providing a substrate having a semiconductor surface (305). For at least one masking level (e.g. gate electrode, contact or via) of the integrated circuit, a mask pattern for the... | 05/08/2012 |
| 8173510 | Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor... | 05/08/2012 |
| 8171804 | Motion conversion system A motion conversion system is described. The motion conversion system comprises a first torsional member operative for rotating in a first direction. A second torsional member is offset a distance from the first torsional member, wherein the second torsional member ... | 05/08/2012 |
| 8157388 | System and method for a projection display system using an optical lightguide A system and method for using an optical lightguide in a projection display system. A plurality of light sources provides a plurality of colored light to a lightguide. The lightguide may include alternating layers of a relatively high refractive index material and a... | 04/17/2012 |
| 8144321 | Encoding optical spectra using a DMD array According to one embodiment of the present invention, a system for encoding an optical spectrum includes a dispersive element, a digital micromirror device (DMD) array, a detector, and a controller. The dispersive element receives light from a source and disperses t... | 03/27/2012 |
| 8139871 | Circuit and method for adaptive, lossless compression of successive digital data An image compression and decompression method compresses data based upon the data states, and decompresses the compressed data based upon the codes generated during the compression. ... | 03/20/2012 |
| 8139284 | Digital micromirror device having wavelength-dependent modulation structure and method of manufacturing the same A digital micromirror device (DMD), a method of manufacturing the DMD and an optical processor incorporating a DMD. In one embodiment, the DMD includes: (1) a first group of micromirrors having a first modulation structure based on a first wavelength of light and a ... | 03/20/2012 |
| 8139078 | Method and system for emulating a display In accordance with one embodiment, a method for emulating the color performance of a display system includes determining an expected first color gamut of the display system. Display data is converted into a format that emulates the first color gamut. The converted d... | 03/20/2012 |
| 8138588 | Package stiffener and a packaged device using the same A package frame for use in packaging microelectromechanical devices and/or spatial light modulators comprises a frame, a stiffener, and a heat dissipater. ... | 03/20/2012 |
| 8138521 | Thyristor semiconductor device and switching method thereof The objective of this invention is to provide a semiconductor device having a thyristor that can shorten the turn-off time. A first electroconductive type first semiconductor region 20 is formed on a substrate, and a second electroconductive type second semic... | 03/20/2012 |
| 8138045 | Method of forming sidewall spacers to reduce formation of recesses in the substrate and increase dopant retention in a semiconductor device A method of forming sidewall spacers for a gate in a semiconductor device includes depositing a gate oxide layer over a gate and source/drain regions, and using a thermal anneal to oxidize silicon of the substrate and silicon of the gate after formation of the depos... | 03/20/2012 |
| 8138035 | Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bon... | 03/20/2012 |
| 8125579 | Polarized light emitting diode and use thereof Provided is a light emitting diode (LED). The LED, in one embodiment, includes a reflective layer located over a substrate and a quarter wave plate emitter layer located over the reflective layer. The quarter wave plate emitter layer, in this embodiment, is substant... | 02/28/2012 |
| 8125558 | Integrated image capture and projection system An integrated system comprises a light valve and an image sensor for image display and image capture. The image sensor and the light valve share a common dual-function lens by positioning the light valve and image sensor at locations offset from the optical axis of ... | 02/28/2012 |
| 8124529 | Semiconductor device fabricated using a metal microstructure control process The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of ... | 02/28/2012 |
| 8124321 | Etching method for use in deep-ultraviolet lithography In a lithography process using an ultraviolet process, the applied ultraviolet resist can be removed by intentionally condensing the ultraviolet resist before removing the ultraviolet resist. ... | 02/28/2012 |
| 8121482 | Spatial light modulator-based reconfigurable optical add-drop multiplexer and method of adding an optical channel using the same A reconfigurable optical add-drop multiplexer (ROADM) and a method of passing at least one optical channel through the multiplexer. In one embodiment, the multiplexer includes: (1) a main input port, (2) a main output port, (3) an add input port, (4) a drop output p... | 02/21/2012 |
| 8120281 | Light beam control system for a spatial light modulator According to one embodiment of the disclosure, a light beam control system includes a positive intrinsic negative diode coupled to a controller circuit. The positive intrinsic negative diode receives a portion of a light beam generated by a light source and converts... | 02/21/2012 |
| 8120155 | Reduced stiction and mechanical memory in MEMS devices A MEMS device is packaged in a process which hydrogen (H) deuterium (D) for reduced stiction. H is exchanged with D by exposing the MEMS device with a deuterium source, such as deuterium gas or heavy water vapor, optionally with the assistance of a direct or downstr... | 02/21/2012 |
| 8119470 | Mitigation of gate to contact capacitance in CMOS flow Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As suc... | 02/21/2012 |
| 8116005 | Light combiner For combining light from different light sources in a light source, dichroic filters are displaced individually according to the physical arrangement of the light sources such that the reflected light from the dichroic filters is coincident in angle and space. ... | 02/14/2012 |
| 8115866 | Method for detecting film pulldown cadences Given an incoming stream of interlaced video, data for each field is analyzed to detect a progressive frame cadence. If a progressive frame cadence is detected, a set of instructions is generated to instruct a de-interlacing unit which fields were mastered from the ... | 02/14/2012 |
| 8114744 | Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wh... | 02/14/2012 |
| 8114731 | Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) loca... | 02/14/2012 |
| 8114729 | Differential poly doping and circuits therefrom A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate... | 02/14/2012 |
| 8114728 | Integration scheme for an NMOS metal gate A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate... | 02/14/2012 |
| 8113662 | System and method for reducing the effect of an image artifact In accordance with the teachings of the present disclosure, a system and method for displaying an image are provided. In one embodiment, the method includes receiving a laser through a rotary diffuser. The rotational speed of the rotary diffuser may be continuously ... | 02/14/2012 |
| 8112737 | Contact resistance and capacitance for semiconductor devices A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical... | 02/07/2012 |
| 8110857 | Low noise JFET A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is le... | 02/07/2012 |
| 8110462 | Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection The present invention relates to electrostatic discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or bre... | 02/07/2012 |
| 8110454 | Methods of forming drain extended transistors A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconduct... | 02/07/2012 |
| 8110416 | AC impedance spectroscopy testing of electrical parametric structures Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spe... | 02/07/2012 |
| 8109485 | Tilting television wall mount A display wall mount comprising a wall bracket configured to couple to a wall and having a first wall bracket edge, a display bracket configured to couple to the display and having a first display bracket edge, and a curvilinear bar moveably coupled between the firs... | 02/07/2012 |
| 8094352 | Mirror assembly with recessed mirror A mirror device and a method for manufacturing the mirror device are presented. The mirror device includes a mirror formed from a first substrate and a hinge/support structure formed from a second substrate. The hinge/support structure includes a recessed region and... | 01/10/2012 |
| 8093716 | Contact fuse which does not touch a metal layer The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse... | 01/10/2012 |
