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| Number | Title | Issue Date |
| 7005938 | Software controllable termination network for high speed backplane bus A line card provides terminating resistors for a bus or traces on a backplane. The line card terminations are activated (connected to ground) by a crossbar switch that is set according to programming (software/firmware/flash memory stored instructions) maintained on... | 02/28/2006 |
| 6636442 | Non-volatile memory element having a cascoded transistor scheme to reduce oxide field stress A non-volatile memory cell (FIG. 3) is provided which includes three transistors, a floating gate non-volatile storage transistor (303) and two cascode connected select transistors (301-302). The two cascoded select transistors (301-302) act together to b... | 10/21/2003 |
| 6622927 | Low voltage thermostat circuit A thermostat circuit (FIG. 4) is provided which (i) works properly with very low supply voltages, (ii) does not need a separate constant value as a reference, and (iii) has improved temperature sensitivity over prior art thermostat circuits. The thermosta... | 09/23/2003 |
| 6525631 | System and method for improved microstrip termination A microstrip termination is provided with a thin film resistor connecting a transmission line to a tapered edge ground, enabling high frequency performance, such as for optical modulators. The tapered edge ground is formed with metal deposited on a substr... | 02/25/2003 |
| 6509821 | Lumped element microwave inductor with windings around tapered poly-iron core A microwave inductor including a coil with windings tapered from a first end of the coil to a second end of the coil to reduce resonant loss glitches found in conventional inductors which have uniform diameter windings. The coil further includes a core co... | 01/21/2003 |
| 6501317 | High speed, low-power CMOS circuit with constant output swing and variable time delay for a voltage controlled oscillator A delay circuit is provided for use in a ring oscillator of a phase locked loop (PLL). The delay circuit includes a differential pair of NMOS transistors 102 and 103 with an NMOS transistor 101 providing the tail current for the differential pair. Complem... | 12/31/2002 |
| 6488403 | Food mixer with whisk attachment A food mixer includes a whipping attachment 60. The attachment includes an elongated impeller 20 that engages a drive of the mixer at the lower surface of a container 10. The attachment also includes a plurality of nested wire-shaped elements 22 attached ... | 12/03/2002 |
| 6448853 | Distortion improvement in amplifiers An improved amplifier includes an input stage differential amplifier (100) with an output forming a gain node (102), an output stage buffer (104) having an input connected to the gain node (102), a compensation capacitor (106) connected from the gain node... | 09/10/2002 |
| 6417703 | Frequency synthesizer using a ratio sum topology A frequency synthesizer including a divide by R frequency divider providing a first input of a phase detector, a divide by N frequency divider providing a second input of the phase detector, and a voltage control oscillator (VCO) receiving the output of t... | 07/09/2002 |
| 6411252 | Narrow band millimeter wave VNA for testing automotive collision avoidance radar components A test system is provided operating in the 76-77 GHz range for testing components of a collision avoidance radar system. The system uses a Scorpion vector network analyzer (VNA) having an internal stimulus source synthesizer operating over a narrow 3-6 GH... | 06/25/2002 |
| 6407622 | Low-voltage bandgap reference circuit A low-voltage reference circuit is provided wherein (i) the output voltage can be set to be a fraction of the silicon bandgap voltage of 1.206 volts, or on the order of 0.9 volts, (ii) the output voltage can have a zero thermal coefficient (TC), and (iii)... | 06/18/2002 |
| 6403447 | Reduced substrate capacitance high performance SOI process A method for forming a semiconductor substrate is provided including the general sequential steps of: providing a handle wafer and a device wafer; implanting at least a first impurity region in a first surface of the device wafer; bonding the first surfac... | 06/11/2002 |
| 6404006 | EEPROM cell with tunneling across entire separated channels An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling tran... | 06/11/2002 |
| 6384683 | High performance intermediate stage circuit for a rail-to-rail input/output CMOS operational amplifier An intermediate stage for a rail-to-rail input/output CMOS opamp includes a floating current source separating two current mirrors (151-154,155-158), where the ideal current source includes a floating current mirror (500,501,502,503,504,505) enabling an o... | 05/07/2002 |
| 6377887 | Caching for pathfinding computation A system for computing a path in an electronic map (or other network) starts a pathfinding exploration in the background while the system is waiting for a request to find a path. The system automatically chooses an origin. The system's memory can be divid... | 04/23/2002 |
| 6335705 | Automotive radar antenna alignment system Two receive antennas integrated with power detectors are used to align the thrust vector of a vehicle to the boresite of an automotive radar antenna mounted upon the vehicle. In the system, a signal is transmitted from the radar antenna to the Radar Test ... | 01/01/2002 |
| 6326808 | Inversion of product term line before or logic in a programmable logic device (PLD) A PLD circuit configuration is provided to use less product term lines than a typical PLD to perform an OR operation without using an OR gate. In one embodiment, an inverter is provided between the output of one product term line and the input of an OR ga... | 12/04/2001 |
| 6316945 | Process for harmonic measurement accuracy enhancement A method for determining the harmonic response of a device under test (DUT) to the input fundamental frequency component of an input signal is performed on a vector network analyzer. A first response of the DUT at the harmonic frequency is obtained by mea... | 11/13/2001 |
| 6266750 | Variable length pipeline with parallel functional units Method and apparatus for implementing a variable length pipeline in a packet-driven memory control system, including a command front end and one or more parallel command sequencers. The command front end decodes an external command packet into an internal... | 07/24/2001 |
| 6169410 | Wafer probe with built in RF frequency conversion module A wafer probe with built in components to perform frequency multiplication, upconversion, downconversion, and mixing typically performed by an RF module of a vector network analyzer (VNA). The wafer probe is designed for testing integrated circuits used i... | 01/02/2001 |
| 6149652 | Spine distraction implant and method A spine distraction implant alleviates pain associated with spinal stenosis and facet arthropathy by expanding the volume in the spine canal and/or neural foramen. The implant provides a spinal extension stop while allowing freedom of spinal flexion.... | 11/21/2000 |
| 6143608 | Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of ... | 11/07/2000 |
| 6127277 | Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.... | 10/03/2000 |
| 6090112 | Spine distraction implant and method A spine distraction implant alleviates pain associated with spinal stenosis and facet arthropathy by expanding the volume in the spine canal and/or neural foramen. The implant provides a spinal extension stop while allowing freedom of spinal flexion.... | 07/18/2000 |
| 6046116 | Method for minimizing the critical dimension growth of a feature on a semiconductor wafer A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backsid... | 04/04/2000 |
| 6016552 | Object striping focusing on data object A technique to stripe a data object that focuses on the data object, but not on the storage media storing the data object. The data object, which can be of any size, is striped into data units at the object level. The technique includes the steps of strip... | 01/18/2000 |
| 6012811 | Eyeglass frames with magnets at bridges for attachment A first frame of an eyeglass device includes a bridge with a magnetic member, and two retaining mechanisms for supporting a pair of lenses. The retaining mechanisms defines a frontal plane. The bridge ties the two retaining mechanism together, with the ma... | 01/11/2000 |
| 6003184 | Automatic swimming pool cleaner An improved swimming pool cleaner of the type for submerged random travel generally along the floor and sidewalls of a swimming pool to dislodge and collect debris. The pool cleaner comprises a frame and associated housing through which a suction mast ext... | 12/21/1999 |
| 5960421 | Service interface repository internationalization A method, apparatus, and article of manufacture for generation of tools and applications for a computer network. An access server, executed by a first computer, accesses interface definitions stored in a database, wherein the object names, short descripti... | 09/28/1999 |
| 5953718 | Research mode for a knowledge base search and retrieval system A research mode in a search and retrieval system generates a research document that infers an answer to a query from multiple documents. The search and retrieval system includes point of view gists for documents to provide a synopsis for a corresponding d... | 09/14/1999 |
| 5946339 | Steelmaking process using direct reduction iron A method and apparatus for producing crude liquid steel using direct reduced iron as a raw material in an electric arc furnace with an acid resistant sidewall refractory lining. In order to effect the more economical melting operation, the electric arc fu... | 08/31/1999 |
| 5946661 | Method and apparatus for identifying and obtaining bottleneck cost information A cycle time method and apparatus is provided to obtain cost, efficiency, bottleneck and value creation information in a manufacturing facility. The manufacturing facility includes a plurality of production lines with each production line including a plur... | 08/31/1999 |
| 5940835 | Methods and apparatus for a universal tracking system A universal tracking system is extremely versatile to permit tracking records in a database for any type of tracking application. A tracking identifier for a database record includes a plurality of fields of equal length. A tracking value, generated for t... | 08/17/1999 |
| 5937319 | Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching A method of fabricating a polysilicon gate 8 in a metal oxide semiconductor (MOS) transistor in an integrated circuit includes providing a metal layer 18, such as cobalt, on the sidewall 12 of the polysilicon gate 8, silicidizing the metal with the polysi... | 08/10/1999 |
| 5930072 | Head-disk assembly for reducing noise coupled into magnetoresistive head preamplifiers A head-disk assembly contains an actuator that includes magnetoresistive heads and a preamplifier. The preamplifier is grounded to the actuator, and the actuator is grounded to a baseplate head-disk assembly via a ground conductor. A first inductive loop,... | 07/27/1999 |
| 5926637 | Service interface repository code generation data A method, apparatus, and article of manufacture for generation of tools and applications for a computer network. An access server, executed by a first computer accesses interface definitions stored in a database. A data access library, coupled to the acce... | 07/20/1999 |
| 5926841 | Segment descriptor cache for a processor A microprocessor having a segment descriptor cache that holds data obtained from a segment descriptor table contained in an external memory and a separate data cache that holds data obtained from portions of the external memory other than the segment desc... | 07/20/1999 |
| 5867430 | Bank architecture for a non-volatile memory enabling simultaneous reading and writing A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address... | 02/02/1999 |
| 5860024 | Microprocessor with automatic name generation including performance indication A microprocessor with automatic and dynamic partname determination including performance number. The microprocessor includes circuitry that measures a core clock frequency for the microprocessor and circuitry that determines a performance indication for t... | 01/12/1999 |
| 5860025 | Precharging an output peripheral for a direct memory access operation A data transfer method with peripheral precharge wherein a starting portion of an output data block targeted for a peripheral is transferred to an output buffer for the peripheral using programmed I/O or slave cycles and wherein a virtual address of the o... | 01/12/1999 |
