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| Number | Title | Issue Date |
| 7926721 | Processing scheme for an indicia reader An apparatus for collecting and processing information bearing indicia (IBI) comprising: a converter for converting light reflected off an IBI into IBI signals representative of the converted light; and, at least one processor adapted for: running at least one appli... | 04/19/2011 |
| 7920831 | PTT/PTS signaling in an internet protocol network Conveying Push-To-Talk and Push-To-Signal (PTT/PTS) information over an IP network through signaling bits defined in and propagated with the Real-Time Protocol (RTP) stream allows the PTT/PTS information to remain synchronized with the voice packets of the stream. T... | 04/05/2011 |
| 7910410 | Integrated low leakage Schottky diode An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N− layer over a P− ... | 03/22/2011 |
| 7906828 | High-voltage integrated circuit device including high-voltage resistant diode A high-voltage integrated circuit includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect... | 03/15/2011 |
| 7902646 | Multiphase synchronous buck converter Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dies and at least nine parallel leads. The dies are electrically connected through a plurality of die attach pads, thus el... | 03/08/2011 |
| 7897471 | Method and apparatus to improve the reliability of the breakdown voltage in high voltage devices A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device. ... | 03/01/2011 |
| 7893548 | SiP substrate Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for re... | 02/22/2011 |
| 7888735 | Integrated complementary low voltage RF-LDMOS Complementary RF LDMOS transistors have gate electrodes over split gate oxides. A source spacer of a second conductivity type extends laterally from the source tap of a first conductivity type to approximately the edge of the gate electrode above the thinnest gate o... | 02/15/2011 |
| 7847395 | Package and package assembly of power device A package and a package assembly for a power device having a high operation voltage and impulse voltage are provided. The package assembly for a power device comprises an assembly wherein the power device is encapsulated and electrically connected to a lead protrudi... | 12/07/2010 |
| 7879534 | Fabrication of a high resolution biological molecule detection device The present invention relates to a method of manufacturing a detection device which involves providing a substrate having a layer of electrically conductive material and a first layer of photosensitive material. Next, the substrate is subjected to a first level phot... | 02/01/2011 |
| 7878879 | Game call assembly A game call assembly for attracting wild game comprises a game call configured for emitting a call when rotated to an inverted position. A motor when energized rotates a shaft. The game call is coupled to the shaft. A switch selectively electrically connects a power... | 02/01/2011 |
| 7863096 | Embedded die package and process flow using a pre-molded carrier An embedded die package includes a carrier with an electrical device in the cavity of the carrier, a first dielectric layer covering the sides and top of the electrical device except for vias over selected bonding pads of the electrical device, a plurality of metal ... | 01/04/2011 |
| 7859057 | Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap dev... | 12/28/2010 |
| 7842968 | Integrated low leakage diode An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to... | 11/30/2010 |
| 7842555 | Integrated transistor module and method of fabricating same An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is ... | 11/30/2010 |
| 7842545 | Semiconductor package having insulated metal substrate and method of fabricating the same Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semi... | 11/30/2010 |
| 7841309 | Gas exchange valve actuator for a valve-controlled internal combustion engine A gas exchange valve actuator for a valve-controlled internal combustion engine is equipped with a rotor, which is to be coupled to a valve member, and a stator, wherein the rotor has at least two stacks, which are arranged at a predetermined distance from one anoth... | 11/30/2010 |
| 7824999 | Method for enhancing field oxide A CMOS device with polysilicon protection tiles is shown in FIG. 2. LOCOS regions 12.1 and 12.2 separate adjacent active regions 16.1 from 16 and 18.1 from 18, respectively. On the upper surface of the LOCOS regions | 11/02/2010 |
| 7816178 | Packaged semiconductor device with dual exposed surfaces and method of manufacturing The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to p... | 10/19/2010 |
| 7812437 | Flip chip MLP with folded heat sink A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat s... | 10/12/2010 |
| 7810021 | Apparatus and method for creating literary macramés By the use of program scripts, databases, and other software elements, taking as input a set of text files making up a work of literature of substantial size, converting the files to an electronically-readable form, linking the files to each other to provide readers... | 10/05/2010 |
| 7808101 | 3D smart power module A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semic... | 10/05/2010 |
| 7807967 | Absorber with hole for metallic magnetic cryogenic detector and aligning method thereof Disclosed herein is an absorber with a hole for a metallic magnetic cryogenic detector and an aligning method. More specifically, the present invention is to provide an absorber with a small hole as an aligning mark for a temperature sensor used in a metallic magnet... | 10/05/2010 |
| 7803676 | Semiconductor device and method of fabricating the same Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed... | 09/28/2010 |
| 7800224 | Power device package A power device package according to the one embodiment of the present invention includes an insulating substrate with an interconnection pattern disposed on the insulating substrate. The interconnection pattern comprises a single conductive layer comprising a first ... | 09/21/2010 |
| 7800179 | High speed, low power consumption, isolated analog CMOS unit A semiconductor device 100 has N-well regions 18 holding PMOS devices 110, 112 and P-type regions 14 holding NMOS devices 114, 116. Devices 110 and 114 have high thresholds and devices 112 and 116 have l... | 09/21/2010 |
| 7795769 | Cover for the motor housing of a ceiling fan A cover for the motor housing of a ceiling fan includes a flexible wrap for covering the motor housing and a magnetic assemblage for attaching the wrap to the motor housing. The cover can be insulating, have an outer decorative surface for aesthetic effects, or both... | 09/14/2010 |
| 7786570 | Heat sink package Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the... | 08/31/2010 |
| 7781835 | Lateral drain MOSFET with improved clamping voltage control A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region... | 08/24/2010 |
| 7777315 | Dual side cooling integrated power device module and methods of manufacture An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second tran... | 08/17/2010 |
| 7768034 | Tapered voltage polysilicon diode electrostatic discharge circuit for power MOSFETs and ICs An electrostatic discharge (ESD) protection network for power MOSFETs includes parallel branches, containing polysilicon zener diodes and resistors, used for protecting the gate from rupture caused by high voltages caused by ESD. The branches may have the same or in... | 08/03/2010 |
| 7750445 | Stacked synchronous buck converter A multichip module buck converter 10 has a high side power mosfet 12, a low side power mosfet 22 and a pre-molded leadframe 40 between the two mosfets for connecting the source of mosfet 12 to the drain of mosfet 22. Clips | 07/06/2010 |
| 7750401 | Self-aligned complementary LDMOS The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces elect... | 07/06/2010 |
| 7745845 | Integrated low leakage schottky diode An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N− layer over a P− ... | 06/29/2010 |
| 7728437 | Semiconductor package form within an encapsulation Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semicondu... | 06/01/2010 |
| 7719453 | Analogue-digital converter using Josephson DAC and method thereof The present invention relates to an analog-to-digital converter (ADC) and an analog-to-digital conversion method employing a Josephson digital-to-analog converter (DAC) into an extremely accurate ADC of a physical metrology grade. The ADC includes: a front end ADC f... | 05/18/2010 |
| 7701048 | Power module for low thermal resistance and method of fabricating the same A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the s... | 04/20/2010 |
| 7682918 | ESD protection for semiconductor products A process for forming a vertical DMOS device with an ESD protection transistor that is configured for carrying a breakdown current includes the steps of masking a substrate of a first polarity type and forming spaced apart surface isolation regions. An insulated gat... | 03/23/2010 |
| 7678656 | Method of fabricating an enhanced resurf HVPMOS device An HV PMOS device formed on a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type includes a pair of field oxide regions on the substrate and at least partially over the HV well. Insulated gates are formed on t... | 03/16/2010 |
| 7659559 | Semiconductor package having insulated metal substrate and method of fabricating the same Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semi... | 02/09/2010 |
