Fisher; John A. - US Patent Attorneys and Agents

Attorney: Fisher; John A.

Number of patents: 139
Last date: July 13, 1993

Browse patents
Browse applications

Number	Title	Issue Date
5227340	Process for fabricating semiconductor devices using a solid reactant source A solid source chemical vapor deposition apparatus and a CVD method for fabricating semiconductor devices are disclosed. In accordance with the process for fabricating semiconductor devices, a CVD reactor chamber having a solid reactant source apparatus c...	07/13/1993
5056875	Container for use within a clean environment A container is provided for use in a clean environment, thereby allowing functional access to items such as chemicals stored within the container while minimizing contamination to the clean environment. A two-part unitary door includes an access plug and ...	10/15/1991
5053357	Method of aligning and mounting an electronic device on a printed circuit board using a flexible substrate having fixed lead arrays thereon An electronic component having a flexible substrate with conductive traces thereon may have the leads separated into arrays that are shaped to contact and be surface mounted to the bonding lands on a printed circuit board (PCB). The flexible substrate, su...	10/01/1991
5021354	Process for manufacturing a semiconductor device A process for the fabrication of CMOS devices is disclosed in which a selectively doped silicon layer is selectively oxidized to provide a differential thickness in the silicon and in the overlaying silicon oxide. In accordance with one embodiment, a semi...	06/04/1991
5014113	Multiple layer lead frame A lead frame having multiple layers permits fine connection to a large number of bonding pads on an electronic component such as an integrated circuit (IC), but strong external package leads. A fully featured or completely extensive lead frame layer bears...	05/07/1991
5012386	High performance overmolded electronic package A package for containing high performance electronic components, such as high speed integrated circuits (ICs). The package bears a substrate of multiple layers having a cavity therein. Leads may be placed within holes in the substrate and soldered or othe...	04/30/1991
5010030	Semiconductor process using selective deposition A process for fabricating semiconductor devices is disclosed which utilizes a selective deposition process to reduce the total number of process steps and especially the total number of photolithography steps required. In accordance with one embodiment of...	04/23/1991
4992388	Short channel IGFET process A process is disclosed for the fabrication of semiconductor devices which yields a device having a very short effective channel length and having polycrystalline source and drain electrodes. In accordance with the disclosed process, a semiconductor substr...	02/12/1991
4988632	Bipolar process using selective silicon deposition A process is disclosed for fabricating bipolar transistors having self aligned and closely spaced polycrystalline silicon base and emitter electrodes. The process is especially amenable to integration with the fabrication of MOS transistors to form BiMOS ...	01/29/1991
4977436	High density DRAM A high density DRAM having a plurality of cells each including a storage capacitor and a single control FET formed together in a trench to substantially reduce planar area of the cell. The FET drain is formed in the upper portion of a pedestal and is acce...	12/11/1990
4966864	Contact structure and method A semiconductor device structure including a contact and a method for its fabrication are disclosed. In accordance with one embodiment of the disclosure, a contact is formed between a monocrystalline silicon substrate and an overlying silicon layer. A sil...	10/30/1990
4948745	Process for elevated source/drain field effect structure A process for the fabrication of elevated source/drain IGFET devices is disclosed. In accordance with one embodiment of the process, a silicon substrate is provided which is divided into active and field regions by a field oxide. A gate oxide is formed ov...	08/14/1990
4948747	Method of making an integrated circuit resistor A process for fabricating an integrated circuit resistor is disclosed. In accordance with one embodiment of that invention a first thin layer of silicon is deposited to overlay a semiconductor substrate. That thin layer of silicon is doped to a predetermi...	08/14/1990
4929565	High/low doping profile for twin well process A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only...	05/29/1990
4928156	N-channel MOS transistors having source/drain regions with germanium Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped dr...	05/22/1990
4918510	Compact CMOS device structure A compact CMOS structure and method for fabricating the structure are disclosed. In one embodiment of the invention the structure includes a P-type surface region in a silicon substrate surrounded by a field oxide which extends, at least in part, above th...	04/17/1990
4914046	Polycrystalline silicon device electrode and method A polycrystalline silicon electrode and method for its fabrication are disclosed. The electrode includes a barrier layer formed by the implantation of carbon, nitrogen, or oxygen ions between two layers of polycrystalline silicon. The lower layer of polyc...	04/03/1990
4912022	Method for sloping the profile of an opening in resist A lithography method for forming an opening in a resist layer with a sloped profile is disclosed which requires no additional processing steps or equipment. A scattering element, for example a ground glass diffuser, is placed in the optical path of radiat...	03/27/1990
4906162	Method for handling semiconductor components A method for handling semiconductor components by utilizing a removable filler strip for temporarily securing or clinching longitudinally arrangeable individual components in a tube, rod or hollow magazine. The filler strip is generally flat, but has surf...	03/06/1990
4897364	Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer An improved LOCOS device isolation method for forming a field oxide is disclosed having the advantage of controllable and uniform sidewall framing of a nutride oxidation mask. This advantage is achieved by the use of a polysilicon layer overlying a nitrid...	01/30/1990
4897602	Electronic device package with peripheral carrier structure of low-cost plastic An electronic device package on a lead frame with a peripheral carrier structure holding the distal ends of the leads in rigid position. The carrier structure is spaced apart from the package body and permits the package to be handled and tested while pro...	01/30/1990
4890144	Integrated circuit trench cell A multiple element integrated circuit trench cell having at least one vertical field effect transistor (FET) in a wall of a trench in a semiconductor substrate. The cell further comprises a central load device within the trench which is electrically conne...	12/26/1989
4889825	High/low doping profile for twin well process A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only...	12/26/1989
4889492	High capacitance trench capacitor and well extension process A process for fabricating high-capacitance trench capacitors in a lightly doped, shallow well of a semiconductor substrate. The process involves a two-step doped glass deposition/diffusion routine. After trench formation into a shallow, lightly doped well...	12/26/1989
4882023	Method and system for producing thin films A method for forming multiple-component thin films using a separate ion cluster beam (ICB) source for each component. Stoichiometry control is provided by measuring the extraction currents across an acceleration voltage and controlling the component suppl...	11/21/1989
4876213	Salicided source/drain structure A process for fabricating a CMOS device using one sidewall spacer for both the source/drain implant and salicide formation, thereby providing an improved salicided source/drain structure. The use of one sidewall spacer for both the source/drain implant an...	10/24/1989
4852062	EPROM device using asymmetrical transistor characteristics An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During p...	07/25/1989
4847213	Process for providing isolation between CMOS devices A process is disclosed for the selective oxidation of MOS devices which preferentially removes implanted field doping from selected silicon substrate regions. In one embodiment, a CMOS substrate is provided with an overlying layer of silicon oxide and a l...	07/11/1989
4836371	Filler strips A filler strip for temporarily securing or clinching longitudinally arrangeable individual components in a tube, rod or hollow magazine. The filler strip is generally flat, but has surface features that serve to press the component against the top, bottom...	06/06/1989
4837184	Process of making an electronic device package with peripheral carrier structure of low-cost plastic An electronic device package on a lead frame with a peripheral carrier structure holding the distal ends of the leads in rigid position. The carrier structure is spaced apart from the package body and permits the package to be handled and tested while pro...	06/06/1989
4837173	N-channel MOS transistors having source/drain regions with germanium Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped dr...	06/06/1989
4835589	Ram cell having trench sidewall load A random access memory (RAM) cell of a trench within a semiconductor substrate. The RAM cell has a load device in the form of a sidewall around at least part of the perimeter of the trench. The load device should be connected to either one of the source/d...	05/30/1989
4835112	CMOS salicide process using germanium implantation A salicided twin-tub CMOS process using germanium implantation to retard the diffusion of the dopants, such as phosphorus and boron. Implantation of n+ and p+ dopants after titanium salicidation is employed to fabricate devices with low junction leakage a...	05/30/1989
4829362	Lead frame with die bond flag for ceramic packages A lead frame having a central die bond flag for ceramic integrated circuit die packages. The direct connection of the die bond flag to the lead frame via one or more leads permits direct connection of the back side or substrate of an integrated circuit di...	05/09/1989
4822753	Method for making a w/tin contact A method is disclosed for fabricating a semiconductor device and especially for contacting a semiconductor device. A silicon substrate is provided which has a device region formed at the surface thereof and which is contacted with a silicide. An insulatin...	04/18/1989
4819040	Epitaxial CMOS by oxygen implantation A technique for selectively implanting regions of semiconductor crystals with oxygen to increase their yield strength. This intentional, selective oxygen pinning technique is especially useful in causing underlying, originally oxygen-free silicon to be mo...	04/04/1989
4811066	Compact multi-state ROM cell A compact, multi-state field effect transistor (FET) cell having a gate with edge portions of a different conductivity type than a central portion of the gate. Both the edge portions and the central portion extend from the source to the drain of the multi...	03/07/1989
4808543	Well Extensions for trench devices A bulge well structure for trench devices in wells of a conductivity type opposite to that of the substrate where the bottom of the trench has localized, extra doping. The additional doping into the bottom of the trench prior to device formation may be im...	02/28/1989
4808555	Multiple step formation of conductive material layers A process of forming a conductive material layer in at least two steps by forming a conductive material layer from a plurality of thin layers of conductive material. The use of a two-step formation process for the conductive material layer permits process...	02/28/1989
4799991	Process for preferentially etching polycrystalline silicon This disclosure relates to a process for etching polycrystalline silicon in preference to single crystal silicon. Polycrystalline silicon is anisotropically etched in a plasma which inclues a noncarbonaceus silicon etching compound such as chlorine togeth...	01/24/1989

«First «Previous1 2 3 4 Next»Last»

PatentStorm

Celebrity Inventors

PatentStorm News

Attorney: Fisher; John A.