Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
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| Number | Title | Issue Date |
| 5495345 | Imaging system with two level dithering using comparator This invention relates to an image processing system which relies upon quantization and dithering techniques to enable an output device, which has a given number of output levels, to accurately reproduce a image which is generated by an input device, whic... | 02/27/1996 |
| 5489162 | Fastening In general, in one aspect, the invention features a fastener having two mating pieces. One of the mating has a rigid surface of thickness q, and a hole in the surface, the hole including a slot defined by two generally parallel edges separated by a distan... | 02/06/1996 |
| 5488716 | Fault tolerant computer system with shadow virtual processor A fault-tolerant computer system has primary and backup computers. Primary and backup virtual machines running on the computers are controlled by corresponding virtual machine monitors. The virtual machines execute only user-mode instructions, while all k... | 01/30/1996 |
| 5479123 | Externally programmable integrated bus terminator for optimizing system bus performance An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference vol... | 12/26/1995 |
| 5454332 | Cash pocket for an automatic teller machine A cash pocket for an automatic teller machine (ATM) comprises a housing having a rear wall with a slot for receiving banknotes from the dispensing mechanism of the ATM into the housing, and a base upon which the dispensed banknotes come to lie upon being ... | 10/03/1995 |
| 5454091 | Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to regist... | 09/26/1995 |
| 5450555 | Register logging in pipelined computer using register log queue of register content changes and base queue of register log queue pointers for respective instructions A pipelined processor has an instruction unit for decoding instructions and pre-processing operands prior to instruction execution, and an execution unit for executing the decoded instructions. The pre-processing of operands includes changes to general pu... | 09/12/1995 |
| 5444717 | Method for providing minimal size test vector sets A method of testing an integrated circuit having a plurality of pins includes the steps of providing a functional test set having an ordered group of test strings wherein each element of the test string is related to one of the pins of said integrated cir... | 08/22/1995 |
| 5428764 | System for radial clock distribution and skew regulation for synchronous clocking of components of a computing system A radial clock distribution system that converts a standard bus clock signal into two pairs of inverted and non-inverted clocking signals. The two pairs of clocking signals have a lower frequency, have a different phase, and are shifted one clock period a... | 06/27/1995 |
| 5426741 | Bus event monitor A monitor for monitoring the occurrence of events on the bus (15) of a multiprocessor computer system. The bus event monitor (BEM) includes a dedicated BEM processor (23) and an event counter subsystem (25). During each bus cycle, the BEM (21) captures an... | 06/20/1995 |
| 5410682 | In-register data manipulation for unaligned byte write using data shift in reduced instruction set processor A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations ... | 04/25/1995 |
| 5406504 | Multiprocessor cache examiner and coherency checker An arrangement for a multiprocessor RISC system enables each CPU of the system to test the control logic of its cache by indirectly examining states of the caches and comparing those states to predetermined valid cache states of the system. The arrangemen... | 04/11/1995 |
