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| Number | Title | Issue Date |
| 8099781 | Method of managing and mitigating security risks through planning An exemplary method is provided for managing and mitigating security risks through planning. A first security-related information of a requested product is received. A second security-related information of resources that are available for producing the requested pr... | 01/17/2012 |
| 7876145 | Control system architecture for qubits A control system architecture for quantum computing includes an array of qubits, which is divided into a plurality of sub-arrays based on a first direction and a second direction, the second direction intersecting the first direction, a plurality of control lines ea... | 01/25/2011 |
| 7870359 | System and method for persistent and robust storage allocation A method for managing computer memory, in accordance with the present invention, includes maintaining multiple sets of free blocks of memory wherein a free block is added to a set based on its size. In response to a request for a block of a request size, a set of bl... | 01/11/2011 |
| 7692561 | Method and apparatus for data decompression in the presence of memory hierarchies A method for decompressing a stream of a compressed data packet includes determining whether first data of a data-dictionary for a first decompression copy operation is located in a history buffer on a remote memory or a local memory, and when it is determined that ... | 04/06/2010 |
| 7566773 | Photolabile compound and substrate for oligomer probe array with the same Provided is a substrate for an oligomer probe array to which a photolabile material having an acetylene derivative is directly attached or attached via a linker. ... | 07/28/2009 |
| 7546491 | Semiconductor memory device with standby current failure judging function and method for judging standby current failure A semiconductor memory device which a pad for receiving a power voltage, a first power line connected to the pad, and a plurality of second power lines respectively connected to memory cells of a repair unit. A selection circuit outputs selection signals for selecti... | 06/09/2009 |
| 7454633 | Integrated circuit card for reducing power consumption An integrated circuit card includes an interface block for performing an interface function with the external devices and a power controller for controlling power of a security integrated circuit for detecting if an operational environment is in an abnormal state, t... | 11/18/2008 |
| 7453750 | Flash memory device with word line discharge unit and data read method thereof Exemplary embodiments of the present invention provide a flash memory device which includes a memory cell array. A decoder circuit is connected to the memory cell array via a plurality of select lines and a plurality of word lines. The detector circuit supplies volt... | 11/18/2008 |
| 7453712 | Hybrid flash memory device and method for assigning reserved blocks thereof A hybrid flash memory device includes an array including a first area and a second area having a larger number of stored bits per cell than the first area. The device includes a hidden area including a first reserved block area and a second reserved block area, wher... | 11/18/2008 |
| 7205969 | Liquid crystal display using swing common electrode voltage and a drive method thereof Disclosed is a liquid crystal display using a swing common electrode voltage and a drive method thereof. The liquid crystal display comprises a timing controller, a data driver, a gate driver outputting gate drive voltages and a drive voltage generator for outputtin... | 04/17/2007 |
| 7205184 | Method of crystallizing silicon film and method of manufacturing thin film transistor liquid crystal display A method of crystallizing a silicon film by which it is possible to obtain a polycrystalline silicon thin film having a uniform crystal structure and a good quality, and a method of manufacturing a thin film transistor-liquid crystal display (TFT-LCD) using the same... | 04/17/2007 |
| 7202522 | Erasable and programmable read only memory (EPROM) cell of an EPROM device and method of manufacturing a semiconductor device having the EPROM cell Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device ha... | 04/10/2007 |
| 7195933 | Semiconductor device having a measuring pattern and a method of measuring the semiconductor device using the measuring pattern A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrate... | 03/27/2007 |
| 7139172 | Apparatus and methods for microchannel cooling of semiconductor integrated circuit packages Apparatus and methods are provided for microchannel cooling of electronic devices such as IC chips, which enable efficient and low operating pressure microchannel cooling of high power density electronic devices having a non-uniform power density distribution, which... | 11/21/2006 |
| 7079674 | Variational approach for the segmentation of the left ventricle in MR cardiac images A system and method for segmenting cardiac images and, in particular, segmenting the left ventricle of the heart using a contour propagation model that integrates visual information and anatomical constraints. The visual information comprises a gradient vector flow-... | 07/18/2006 |
| 7020316 | Vessel-feeding pulmonary nodule detection by volume projection analysis A system and method for automatically detecting nodules from images include a seed point generation unit for generating a seed point from a plurality of images that define a volume, a volume of interest generation unit for defining a volume of interest comprising th... | 03/28/2006 |
| 7016257 | Semiconductor memory device capable of generating variable clock signals according to modes of operation A semiconductor memory device comprising: an array of memory cells; an address input circuit for receiving an external address in response to an address clock signal; a selecting circuit for selecting a memory cell in response to an address output from the address i... | 03/21/2006 |
| 6961454 | System and method for segmenting the left ventricle in a cardiac MR image A method is provided for segmenting a magnetic resonance image of interest of a left ventricle. The method includes determining a myocardium contour according to a graph cut of candidate endocardium contours, and a spline fitting to candidate epicardium contours in ... | 11/01/2005 |
| 6924207 | Method of fabricating a metal-insulator-metal capacitor A method of fabricating a semiconductor device is provided. The method includes forming an interconnection line over a ssubstrate. The interconnection line functions as a first electrode. A first insulating layer is formed on the substrate including the metal interc... | 08/02/2005 |
| 6823456 | System and method for providing trusted services via trusted server agents A client/server networking topology comprising a trusted server agent (TSA) (e.g., software application) that runs either at a client node or at a node in close proximity to the client and provides various trusted services to the client on behalf of a trusted server... | 11/23/2004 |
| 6800418 | Fluorine-containing photosensitive polymer having hydrate structure and resist composition comprising the same Provided are a fluorine-containing photosensitive polymer having a hydrate structure and a resist composition including the photosensitive polymer. The photosensitive polymer has an average molecular weight of about 3,000-100,000 with a repeating unit including a gr... | 10/05/2004 |
| 6657264 | Layout method of latch-up prevention circuit of a semiconductor device A layout method is provided for a latch-up prevention circuit of a semiconductor memory device which includes the steps of: arranging a cell array at substantially the middle of the device; placing peripheral circuits next to both sides of the cell array;... | 12/02/2003 |
