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| Number | Title | Issue Date |
| 6037804 | Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output... | 03/14/2000 |
| 5930148 | Method and system for verifying a digital circuit design including dynamic circuit cells that utilize diverse circuit techniques A method and system are described, which utilize timing analysis to verify a digital circuit design that includes a plurality of dynamic logic circuit cells employing diverse circuit techniques and that may also include static logic circuit cells. For eac... | 07/27/1999 |
| 5887183 | Method and system in a data processing system for loading and storing vectors in a plurality of modes A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface... | 03/23/1999 |
| 5809268 | Method and system for tracking resource allocation within a processor A method and system are disclosed for tracking the allocation of resources within a processor having multiple execution units which support speculative execution of instructions. The processor includes a resource counter including a first counter and a se... | 09/15/1998 |
| 5767717 | High performance dynamic logic compatible and scannable transparent latch A high performance dynamic logic compatible transparent latch is provided. The latch comprises a first switchable invertor circuit, a second invertor circuit, and a third switchable invertor circuit. The first invertor, having a data input, a clock input ... | 06/16/1998 |
| 5764549 | Fast floating point result alignment apparatus A device for aligning the radix point of an unaligned binary result of a floating point operation to a normalized or denormalized position is provided. The device comprises an alignment circuit that produces a shift alignment vector indicating the positio... | 06/09/1998 |
| 5706237 | Self-restore circuit with soft error protection for dynamic logic circuits An improved self-restore circuit and method for restoring the output line of a dynamic logic circuit. The self-restore circuit includes two transistors connected in series between the output line and the reference voltage node. The first transistor activa... | 01/06/1998 |
