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| Number | Title | Issue Date |
| 7769607 | Method of enhancing value of pension plan assets A method for increasing the assets of a pension plan is disclosed. The method includes investing at least a portion of one or more assets of a pension plan so as to acquire an interest in one or more current, in-force insurance contracts from one or more owners of t... | 08/03/2010 |
| 7640126 | Combine-information processing apparatus, method for processing combine-information, program, and recording medium An inspectional equation storage unit 103 for storing an inspectional equation calculating one or more principal component scores, the inspectional equation being obtained by performing a principal component analysis on measured data on a plurality of measuri... | 12/29/2009 |
| 4897154 | Post dry-etch cleaning method for restoring wafer properties A post dry etching process for restoring wafers damaged by dry etching such as RIE, comprising the steps of removing any dry etch residue layer from the etched portions of the wafer and forming an oxide on those etched portions; rapid thermal annealing th... | 01/30/1990 |
| 4856000 | Duplicated circuit arrangement for fast transmission and repairability Duplicated circuit arrangement comprising a main processor (30) and its P bit data bus (44), and two identical redundant devices (21:22), each device is comprised of a processing element (23;35) performing the same task in parallel on a P bits word, and s... | 08/08/1989 |
| 4852096 | CN2 test pattern generator A CN2 memory testing circuit for generating a sequence of C(N2 +1) memory addresses which will accomplish a CN2 test with the least possible memory transitions. In one embodiment for an odd integer C, the mth bit in the me... | 07/25/1989 |
| 4846920 | Plasma amplified photoelectron process endpoint detection apparatus A plasma processing apparatus and process endpoint detection method including a plasma chamber for processing an item that has a first portion of a first material and a second portion of a second material, with the first and second materials having differ... | 07/11/1989 |
| 4839715 | Chip contacts without oxide discontinuities An integrated circuit chip including a first and a higher second surface levels with an abrupt sidewall step transition therebetween, and having a first layer of a first conductive material disposed over the first surface level and over the second surface... | 06/13/1989 |
| 4832787 | Gas mixture and method for anisotropic selective etch of nitride A gas mixture for use in the selective dry etching of a nitride insulator layer relative to an oxide insulator layer comprising: a gas mixture containing chlorine and oxygen. The oxygen in this gas mixture must comprise 15% or less by volume. In a preferr... | 05/23/1989 |
| 4833425 | Analog macro embedded in a digital gate array A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the log... | 05/23/1989 |
| 4825178 | Oscillator with noise rejection and square wave output An oscillator with noise rejection which may be used in a gate array in a semiconductor chip including a first amplifier circuit, a circuit, for connecting an external feedback element (crystal) across the input and inverting output of the first amplifier... | 04/25/1989 |
| 4824009 | Process for braze attachment of electronic package members In the process of braze attachment of electronic package members, such as attaching metallic coated connector pins to a multilayer ceramic substrate, contact areas of the substrate are formed by sequential coatings of molybdenum and nickel, which are heat... | 04/25/1989 |
| 4810962 | Voltage regulator capable of sinking current A voltage regulator for regulating the voltage at a first node, comprising a first voltage supply; a first node; a first transistor with a control terminal connected to the first node; a circuit for varying the VBE voltage drop of the first transistor in accordance... | 03/07/1989 |
| 4811343 | On-chip on-line AC and DC clock tree error detection system A test circuit for producing a "fail" signal if a clock path driver circuit develops an AC or DC defect. In the simplest embodiment, this test circuit comprises a time delay block for providing a delayed clock signal and its complement, with a delay that ... | 03/07/1989 |
| 4809196 | Method for designating/sorting semiconductor wafers according to predicted oxygen precipitation behavior A method for marking/sorting semiconductor wafers in accordance with predicted values of oxygen precipitation in the wafers that will occur after the performance of a thermal process step. In a preferred embodiment, this oxygen precipitation prediction is... | 02/28/1989 |
| 4806785 | Half current switch with feedback A half current switch comprising: at least one input transistor, a load resistance connected between a first voltage reference and the collector of the input transistor, a constant-current resistance connected between the emitter of the input transistor a... | 02/21/1989 |
| 4798976 | Logic redundancy circuit scheme A logic redundancy circuit scheme, comprising a plurality of pairs of logic circuit groups, each logic circuit group in a given pair having a respective logic node and a respective power control line, with each logic circuit group in a given pair generati... | 01/17/1989 |
| 4774559 | Integrated circuit chip structure wiring and circuitry for driving highly capacitive on chip wiring nets The disclosure is directed to integrated circuit chips and particularly to "gate array", or "master slices" whereon one or more circuits drive a highly capacitive on chip wiring net. The driving circuits are modified and a compensation circuit coupled to ... | 09/27/1988 |
| 4766399 | Oscillator circuit An oscillator with noise rejection and a fifty percent duty cycle for the on-chip generation and conversion of a sine wave to a square wave, using an external reference crystal. The circuit comprises a low gain current switch including a first and second ... | 08/23/1988 |
| 4752813 | Schottky diode and ohmic contact metallurgy A Schottky barrier diode and ohmic contact metallurgy which is especially suited for shallow-junction bipolar semiconductor devices. The metallurgy comprises a thin layer of an at least 95 atomic % pure Schottky metal disposed in the contact openings on a... | 06/21/1988 |
| 4746817 | BIFET logic circuit A BIFET logic circuit for quickly switching an output line from a high level to a reference level. The BICMOS circuit comprises a push-pull circuit including a first bipolar transistor for driving current into an output line, and a second bipolar transist... | 05/24/1988 |
| 4746815 | Electronic EC for minimizing EC pads A specially designed module and integrated circuit chip therefor which permits the sharing of module EC pads between chip receiver and driver circuits. The chip has a direct normal input line to each receiver circuit therein and a direct normal output lin... | 05/24/1988 |
| 4743781 | Dotting circuit with inhibit function A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs, while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the colle... | 05/10/1988 |
| 4740968 | ECC circuit failure detector/quick word verifier A circuit for quickly determining if all of the data bits in an ECC word are correct and/or for detecting failures in an error detection syndrome generation path in an ECC circuit, where the ECC circuit utilizes an error correction code with two diagonal ... | 04/26/1988 |
| 4731158 | High rate laser etching technique A method and means for high-rate etching a material is disclosed including the steps of disposing a gas mixture of a fluorine-containing molecule and H2 over the surface of a material to be etched; and laser dissociating this fluorine-containin... | 03/15/1988 |
| 4728814 | Transistor inverse mode impulse generator An impulse generator for detecting an edge of an input pulse. The impulse generator comprises a first and second transistors connected to turn on at the occurrence of a signal pulse on an input line, with the second transistor connected to operate in its ... | 03/01/1988 |
| 4729006 | Sidewall spacers for CMOS circuit stress relief/isolation and method for making A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low ... | 03/01/1988 |
| 4721689 | Method for simultaneously forming an interconnection level and via studs A method for simultaneously forming a level of interconnection metallurgy over, and inter-level via studs through, an insulating layer of a semiconductor chip. The method comprises the steps of forming a plurality of via holes in the insulating layer, hig... | 01/26/1988 |
| 4713140 | Laser luminescence monitor for material thickness An apparatus and method for monitoring a change of thickness of a first material with a first bandgap energy, for disposal over a second material on a wafer and having a second different bandgap energy, wherein at least one of the materials has a direct b... | 12/15/1987 |
| 4708941 | Optical waveguide sensor for methane gas A device for detecting small amounts of alkanes such as methane, ethane, propane, and butane gases, comprising an optical waveguide and a light source for propagating light therethrough; apparatus for obtaining samples of air to be tested; apparatus for a... | 11/24/1987 |
| 4709169 | Logic level control for current switch emitter follower logic A logic circuit network with circuitry for independently controlling at least one of the logic levels generated thereby, comprising, in one embodiment, a logic circuit with an output current node, a complement output current node, and at least one input l... | 11/24/1987 |
| 4694433 | Semiconductor memory having subarrays and partial word lines A memory structure for very large memory arrays on a chip is described where the memory array is divided into a number of subarrays. The subarrays are controlled via common word decoders and subarray decoders. The word lines of the individual subarrays ar... | 09/15/1987 |
| 4684339 | Gas-loaded pressure diaphragm A gas-loaded diaphragm for exerting a predetermined pressure on a ceramic substrate during sintering to prevent x-y shrinkage. In the most preferred embodiment, the diaphragm comprises a gas-filled base composed of two opposing discs, and a substantially ... | 08/04/1987 |
| 4678267 | Parabolic optical waveguide horns and design thereof Coupling between narrow-and wide-channel optical waveguides is found to be very efficiently performed by coupling regions in the form of parabolas. Design equations for parabolic coupling regions are given.... | 07/07/1987 |
| 4675072 | Trench etch endpoint detection by LIF Laser induced fluorescence is utilized to detect and control the reactive ion etch-through of a given layer in a wafer by detecting a large change in the concentration of a selected minor species from the wafer in the etching plasma. This selected minor s... | 06/23/1987 |
| 4661789 | Microwave recursive filter A broadband microwave recursive filter that provides sharp transitions in the frequency domain between adjacent stop and passbands comprising a signal input node; a signal output node; a filter circuit connected between the signal input node and the signa... | 04/28/1987 |
| 4659423 | Semiconductor crystal growth via variable melt rotation An improvement in the method and apparatus for growing a semiconductor crystal by the Czochralski technique comprising the steps of applying a rotating transverse magnetic field to molten semiconductor material held in a crucible during the seed crystal p... | 04/21/1987 |
| 4650329 | Optical 3-d signature device for detecting chemical agents An optical device for obtaining a 3-dimensional signature or a plurality of 2-dimensional signatures for a given sample in order to detect predetermined chemical agents. The device comprises a light channel with a first sensing optical fiber with a coatin... | 03/17/1987 |
| 4641170 | Self-aligned lateral bipolar transistors An integrated circuit structure which includes small area lateral bipolar and method for making the same is described. A semiconductor body, such as a monocrystalline silicon wafer, having surface regions thereof isolated from other such regions by a patt... | 02/03/1987 |
| 4636834 | Submicron FET structure and method of making A method for making contact to a small area field effect transistor device is described. A monocrystalline semiconductor body having at least a surface region of a first conductivity is provided with a insulating layer over the surface region. A substanti... | 01/13/1987 |
| 4634230 | Multi dimensional instantaneous optical signal processor A 3 or more - dimensional optical processor for simultaneously processing ree or more parameters from a coherent emitter via an acoustic Bragg cell. For a 3-D processor, two separate antenna arrays (azimuth and elevation) are connected to excite two sets ... | 01/06/1987 |
