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| Number | Title | Issue Date |
| 7747971 | State retention for formal verification Verification model of static state retention behavior of a state saving element design during power shut off of the state saving element in an integrated circuit design including: creating in a computer readable medium a model of a single edge triggered state saving... | 06/29/2010 |
| 7739642 | Optimizing integrated circuit design through balanced combinational slack plus sequential slack A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of re... | 06/15/2010 |
| 7739629 | Method and mechanism for implementing electronic designs having power information specifications background A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of... | 06/15/2010 |
| 7735048 | Achieving fast parasitic closure in a radio frequency integrated circuit synthesis flow Methods achieve fast parasitic closure in IC (integrated circuit) synthesis flow with particular application to RFIC (radio frequency integrated circuit) synthesis flow. Parasitic corners generated based on earlier layout statistics are incorporated into circuit res... | 06/08/2010 |
| 7735036 | System and method enabling circuit topology recognition with auto-interactive constraint application and smart checking A computer-implemented method of identifying sub-circuits in circuit designs includes: receiving a selection of a sub-circuit; specifying a match expression for the sub-circuit, where the match expression characterizes matching properties of components of the sub-ci... | 06/08/2010 |
| 7735030 | Simulating restorable registers in power domain systems A method of simulating a restorable register in a power domain of an RTL (register transfer level) design includes: specifying the power domain in the RTL design, wherein the power domain includes one or more registers and is configured to change power levels separa... | 06/08/2010 |
| 7711536 | System and method for verification aware synthesis A method of synthesis of a model representing a design of an integrated circuit is provided including associating a test environment with a first model representing a design of an integrated circuit; translating the first model of the design to a second model of the... | 05/04/2010 |
| 7694251 | Method and system for verifying power specifications of a low power design Method and system for verifying power specifications of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of the low power design, receiving a power specification file for describing power requirem... | 04/06/2010 |
| 7600211 | Toggle equivalence preserving logic synthesis A method of synthesis of a second circuit (N2) that is toggle equivalent to a first circuit (N1), comprising building up N2 in topological order, starting from the input side of N2, by producing a sequence of subcircuit de... | 10/06/2009 |
| 7596770 | Temporal decomposition for design and verification Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machin... | 09/29/2009 |
| 7587687 | System and method for incremental synthesis A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a lev... | 09/08/2009 |
| 7579886 | Phase locked loop with adaptive phase error compensation An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and... | 08/25/2009 |
| 7574342 | Methods of model compilation for models used in an electronic circuit simulator A method is provided for compiling a model for use in a simulation, the method comprising receiving a description of the model; and automatically converting the description into an implementation of the model that is customized for a selected analysis during simulat... | 08/11/2009 |
| 7562323 | System, method and computer program product for handling small aggressors in signal integrity analysis A method, system and computer program product for determining aggressor-induced crosstalk in a victim net of a stage of an integrated circuit design is provided. The methodology can include combining a plurality of aggressor nets to construct a virtual aggressor net... | 07/14/2009 |
| 7559040 | Optimization of combinational logic synthesis through clock latency scheduling In optimizing a design of an integrated circuit, an iteration of a logic optimization process is performed that at least partially optimizes a circuit design such that there is slack remaining in one or more combinational logic paths in the circuit design following ... | 07/07/2009 |
| 7551985 | Method and apparatus for power consumption optimization for integrated circuits Method and apparatus for finding an assignment of voltages to all power domains of an integrated circuit such that the power consumption of an integrated circuit design is minimized and timing requirements (signal propagation delay or slack) are met. This is done by... | 06/23/2009 |
| 7530047 | Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the circuit design; specifying at least one constraint upon the overall circui... | 05/05/2009 |
| 7524710 | Radiation-hardened silicon-on-insulator CMOS device, and method of making the same A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire... | 04/28/2009 |
| 7472361 | System and method for generating a plurality of models at different levels of abstraction from a single master model A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at diffe... | 12/30/2008 |
| 7466191 | Self reverse bias low-power high-performance storage circuitry and related methods An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coup... | 12/16/2008 |
| 7467116 | Incremental data fusion and decision making system and associated method A computer implemented adaptive ensemble classifier is provided which includes: a plurality of classifiers; a decision structure that maps respective classifier combinations to respective classification decision results; and a plurality of respective sets of weights... | 12/16/2008 |
| 7416341 | Capillary reservoir for FDB motors For a motor having fluid dynamic bearing(s) defined by surfaces of relatively rotatable motor members, aspects include providing a capillary reservoir between relatively irrotatable surfaces. The capillary reservoir may comprise a tapering gap that is vented to a ga... | 08/26/2008 |
| 7411250 | Radiation-hardened silicon-on-insulator CMOS device, and method of making the same A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire... | 08/12/2008 |
| 7390125 | Single piece hub with integral upper and lower female cones To simplify fabrication of an integral hub piece, the opening between the upper and lower female cones in this hub has sufficient width or radial dimension to allow access to both cones from one side of the hub with the cutting tool. A cutting tool is used which has... | 06/24/2008 |
| 7378771 | FDB motor with tapered shaft for improved pumping efficiency For motors having a journal with one or more groove regions and a shaft for relative rotation in the journal, aspects include providing a dual tapered shaft. The shaft may be tapered by the application of a wear resistant coating at least opposite the groove regions... | 05/27/2008 |
| 7372663 | Lubricated limiter for fluid dynamic bearing motor In one example, a FDB motor having a top-cover attached, EM biased bearing system is provided. The motor includes a shaft and rotor disposed for relative rotation, and an axial limiter for restricting axial movement of the rotor with respect to the shaft, wherein th... | 05/13/2008 |
| 7362022 | Column capillary seal for FDB motors For a motor having liquid lubricated bearing surface(s), aspects include providing a column shaped Capillary Seal (CS) for storing and supply lubricating liquid to the bearing surface(s). The column shaped CS may have a cross-section substantially topologically equi... | 04/22/2008 |
| 7359843 | Robust calculation of crosstalk delay change in integrated circuit design A method of delay change determination in an integrated circuit design including a stage with a victim net and one or more aggressor nets capacitively coupled thereto, the method comprising: determining a nominal (noiseless) victim net signal transition; determining... | 04/15/2008 |
| 7350308 | Sleeve cone angle measurement system For repeatably and accurately measuring characteristics of workpieces, such angle of taper of a conical cavity defined by a workpiece, examples may include a system having a stage movable in predictable and repeatable increments, and a compliancy fixture. The compli... | 04/01/2008 |
| 7327531 | Two-plane balance for spindle motors In a spindle hub configured for rotation about an axis, through holes extend from a first end of the spindle hub to a second end of the spindle hub. The through holes are generally parallel to the axis. A method of achieving two-plane balance of a disc pack assembly... | 02/05/2008 |
| 7284909 | Hybrid orbital fluid dynamic bearing motor Hybrid orbital fluid dynamic bearing motors are disclosed. The motors achieve improved efficiency advantages observed in fluid dynamic bearing motors containing an orbital ring. In addition, the hybrid orbital FDB motor has serial thrust bearings and traditional sty... | 10/23/2007 |
| 7284910 | Capillary seal with flow restrictors A disk drive motor having a capillary bearing seal is provided. In one embodiment, a disk drive motor includes a stationary assembly and a rotating assembly having a fluid dynamic journal bearing disposed therebetween. A capillary seal is defined proximate an upper ... | 10/23/2007 |
| 7242810 | Multimodal high-dimensional data fusion for classification and identification A method is provided for evaluating identity of an object, the method including: converting feature information representing the object to a plurality of mathematically defined components; grouping the components into multiple modalities; producing respective first ... | 07/10/2007 |
| 7239477 | Low profile air-oil hybrid fluid dynamic bearing motor A short form fluid dynamic bearing motor is provided comprising a stationary shaft attached at a first end to a motor cover, a plate supported on a second end of the shaft, a hub rotatably supported on the shaft, a journal gap defined between an outer diameter of th... | 07/03/2007 |
| 7234868 | Radial pumping oil seal for fluid dynamic bearing motor An improved rotational motor, such as a spindle motor for a disc drive, is provided. The motor first comprises a hub having a shaft portion and a horizontal body portion. The motor also comprises a sleeve surrounding the shaft portion of the hub. A fine first vertic... | 06/26/2007 |
| 5742640 | Method and apparatus to improve PSTN access to wireless subscribers using a low bit rate system A method of cellular communication among a subscriber unit, a base station and a switch controller is provided which comprises the steps of digitally encoding speech signals at the subscriber unit; generating radio forward error correction (FEC) at the su... | 04/21/1998 |
| 4742493 | Multiple port memory array device including improved timing and associated method An integrated circuit device which includes a memory array comprising a plurality of respective memory locations for storing binary data, each respective memory location corresponding to a respective combination of binary address signals, the device furth... | 05/03/1988 |
| 4740971 | Tag buffer with testing capability A tag buffer having built-in testing capabilities is disclosed. In a single-chip, integrated-circuit design which includes a SRAM, a parity generator and checker, and a comparator, a method and capability of testing the functionality of the SRAM and parit... | 04/26/1988 |
| 4731758 | Dual array memory with inter-array bi-directional data transfer A high access speed memory for the internal storage of data and the addressable input/output transfer of data thereto, the memory comprising means for the dynamic storage of data, means for the static storage of data, and means for transferring data betwe... | 03/15/1988 |
| 4722822 | Column-current multiplexing driver circuit for high density proms Current switches are used to control current into the columns during READ operations of a PROM. The circuit provides one such switch for each of the columns of the PROM and makes possible the use of a single current source which is connected to each of th... | 02/02/1988 |
