Did You Know...
...that on Dec. 15, 1836, the Patent Office was completely destroyed by fire? Lost were some 7,000 models, 9,000 drawings, and 230 books plus all records of patent applications and grants.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5825679 | Fast sign extend for multiplier array sums and carrys A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes lo... | 10/20/1998 |
| 5778423 | Prefetch instruction for improving performance in reduced instruction set processor A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations ... | 07/07/1998 |
| 5742537 | Fast determination of floating point sticky bit from input operands A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky... | 04/21/1998 |
| 5740357 | Generic fault management of a computer system A method of managing faults in a computer system including the steps of detecting an error, handling the error along a functional hierarchy and, further, handling a fault that caused the error in a management hierarchy which can be operated separately fro... | 04/14/1998 |
| 5729485 | Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes lo... | 03/17/1998 |
| 5726927 | Multiply pipe round adder A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes lo... | 03/10/1998 |
| 5717729 | Low skew remote absolute delay regulator chip A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a clock repeater chip, a module transmission network and a ... | 02/10/1998 |
| 5694579 | Using pre-analysis and a 2-state optimistic model to reduce computation in transistor circuit simulation Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the logic design being subject to resistive conflicts and to cha... | 12/02/1997 |
| 5694350 | Rounding adder for floating point processor A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky... | 12/02/1997 |
| 5687310 | System for generating error signal to indicate mismatch in commands and preventing processing data associated with the received commands when mismatch command has been determined An apparatus which provides a means of ensuring command synchronization for computer systems employing sliced gate array processors includes a computer bus, a plurality of central processing units and a plurality of input/output processors coupled to the ... | 11/11/1997 |
| 5680584 | Simulator system for code execution and debugging within a multi-architecture environment A computer system embodies a first hardware (X) architecture for providing an X domain for an X code. The computer system includes a system for simulating a second hardware (Y) architecture providing a Y domain for Y code and for executing the Y code, and... | 10/21/1997 |
| 5678045 | Method and apparatus for multiscript access to entries in a directory A system and method for providing multiscript aliasing of, and access to name entries in a directory information tree (DIT) stored in one or more Directory Service Agent (DSA) servers, such as in a distributed DIT. Where DIT original entry objects are exp... | 10/14/1997 |
