Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
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| Number | Title | Issue Date |
| 8176347 | Microprocessor that performs adaptive power throttling A microprocessor that performs adaptive power throttling includes a calculation unit configured to calculate an average power consumed by the microprocessor over a most recent predetermined sample time and to determine whether the average power is less than a predet... | 05/08/2012 |
| 8161246 | Prefetching of next physically sequential cache line after cache line that includes loaded page table entry A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that includes an indicator that the load request is loading a page table entry. The prefetch unit is configure... | 04/17/2012 |
| 8145890 | Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user program includes a conditional branch instruction. A first fetch unit fe... | 03/27/2012 |
| 8135970 | Microprocessor that performs adaptive power throttling A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined ma... | 03/13/2012 |
| 8131984 | Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in th... | 03/06/2012 |
| 8108624 | Data cache with modified bit array A microprocessor includes first and second functional units and a data cache having a data array having a write port, a modified bit array having a read port and a write port, and a tag array having a read port, each array having the corresponding predetermined orga... | 01/31/2012 |
| 8108621 | Data cache with modified bit array A cache memory system includes a first array of storage elements each configured to store a cache line, a second array of storage elements corresponding to the first array of storage elements each configured to store a first partial status of the cache line in the c... | 01/31/2012 |
| 8090931 | Microprocessor with fused store address/store data microinstruction A microprocessor includes an instruction translator that translates PUSHF, POP, and MOVSB x86 macroinstructions into multiple microinstructions that include a fused store microinstruction. For PUSHF, first and second microinstructions moves the x86 EFLAGS register i... | 01/03/2012 |
| 8074105 | High data availability SAS-based RAID system A storage system includes two RAID controllers, each having two SAS initiators coupled to a zoning SAS expander. The expanders are linked by an inter-controller link and create a SAS ZPSDS. The expanders have PHY-to-zone mappings and zone permissions to create two d... | 12/06/2011 |
| 8074060 | Out-of-order execution microprocessor that selectively initiates instruction retirement early A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instru... | 12/06/2011 |
| 8069340 | Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions A microprocessor instruction translator translates a macroinstruction into three microinstructions to perform a read/modify/write operation on a memory operand. A first microinstruction instructs the microprocessor to calculate a source address and to load the memor... | 11/29/2011 |
| 8069339 | Microprocessor with microinstruction-specifiable non-architectural condition code flag register A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plur... | 11/29/2011 |
| 8051116 | Apparatus and method for generating packed sum of absolute differences A method for executing an MMX PSADBW instruction by a microprocessor. The method includes generating packed differences of packed operands of the instruction and generating borrow bits associated with each of the packed differences; for each of the packed difference... | 11/01/2011 |
| 8046400 | Apparatus and method for optimizing the performance of x87 floating point addition instructions in a microprocessor A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and generates a sum from its addends. The FPU determines whether any condition... | 10/25/2011 |
| 8013649 | Dynamic clock feedback latch A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first t... | 09/06/2011 |
| 8006014 | PCI-Express data link transmitter employing a plurality of dynamically selectable data transmission priority rules A PCI-Express data link transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one of multiple scheduled TLPs and DLLPs based on their distinct types. A selector selects one of the arbiters to select the one of the multiple s... | 08/23/2011 |
| 7996650 | Microprocessor that performs speculative tablewalks A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory whose physical address speci... | 08/09/2011 |
| 7996586 | USB port for employing a plurality of selectable data transmission priority rules A USB port transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one USB transmission from among multiple scheduled USB transmissions based on their types. A selector selects one of the arbiters to select the one USB transmi... | 08/09/2011 |
| 7979675 | Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution A microprocessor includes a register that stores a state and a fetch unit that fetches instructions of a program. The program includes a first instruction followed non-immediately by a second instruction. The first instruction instructs the microprocessor to update ... | 07/12/2011 |
| 7975132 | Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and d... | 07/05/2011 |
| 7937561 | Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture A microprocessor processes a macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register. An instruction translator translates the macroinstruction into a merge microinstructio... | 05/03/2011 |
| 7917568 | X87 fused multiply-add instruction An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the... | 03/29/2011 |
| 7849120 | Microprocessor with random number generator and instruction for storing random data A microprocessor includes a random number generator circuit (RNG) within its instruction set architecture (ISA). An RNG buffer accumulates zero or more bytes of random data generated by the RNG. An RNG counter maintains a count of the accumulated random data bytes. ... | 12/07/2010 |
| 7827390 | Microprocessor with private microcode RAM A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macr... | 11/02/2010 |
| 7818358 | Microprocessor with random number generator and instruction for storing random data A microprocessor includes a storage element that accumulates a variable number of bytes of random data. The microprocessor also includes a counter that maintains a count of the variable number of bytes accumulated in the storage element. The microprocessor also incl... | 10/19/2010 |
| 7814350 | Microprocessor with improved thermal monitoring and protection mechanism A microprocessor control circuit continuously monitors core logic operating temperature and detects it has risen above a first temperature and responsively iteratively controls a system voltage source to output a next lower one of its N output voltage levels and con... | 10/12/2010 |
| 7809886 | RAID controller using capacitor energy source to flush volatile cache data to non-volatile memory during main power outage A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is su... | 10/05/2010 |
| 7802078 | REP MOVE string instruction execution by selecting loop microinstruction sequence or unrolled sequence based on flag state indicative of low count repeat A microprocessor REP MOVS macroinstruction specifies the word length of the string in the IA-32 ECX register. The microprocessor includes a memory, configured to store a first and second sequence of microinstructions. The first sequence conditionally transfers contr... | 09/21/2010 |
| 7788541 | Apparatus and method for identifying disk drives with unreported data corruption A RAID controller uses a method to identify a storage device of a redundant array of storage devices that is returning corrupt data to the RAID controller. The method includes reading data from a location of each storage device in the redundant array a first time, a... | 08/31/2010 |
| 7774627 | Microprocessor capable of dynamically increasing its performance in response to varying operating temperature A temperature sensor in a microprocessor monitors its operating temperature Operating point data includes a first temperature being the maximum temperature at which the microprocessor will reliably operate at a first frequency and first voltage, the first frequency ... | 08/10/2010 |
| 7770042 | Microprocessor with improved performance during P-state transitions A microprocessor includes core logic that operates according to a core clock signal in order to execute program instructions, clock generation circuitry controllable to generate the core clock signal having one of N different possible frequencies, wherein N is more ... | 08/03/2010 |
| 7712105 | Microprocessor including random number generator supporting operating system-independent multitasking operation A microprocessor that includes a random number generator (RNG) that saves and restores its own state on a task switch without operating system (OS) support. The RNG includes a control and status register (CSR) for storing control values that affect the generation of... | 05/04/2010 |
| 7711989 | Storage system with automatic redundant code component failure detection, notification, and repair A RAID system includes a non-volatile memory storing a first program and first and second copies of a second program, and a processor executing the first program. The first program detects the first copy of the second program is failed and repairs the failed first c... | 05/04/2010 |
| 7707397 | Variable group associativity branch target address cache delivering multiple target addresses per cache line A branch prediction apparatus having two two-way set associative cache memories each indexed by a lower portion of an instruction cache fetch address is disclosed. The index selects a group of four entries, one from each way of each cache. Each entry stores a single... | 04/27/2010 |
| 7698583 | Microprocessor capable of dynamically reducing its power consumption in response to varying operating temperature A microprocessor capable of dynamically reducing its power consumption based on its varying operating temperature includes a temperature sensor that monitors the microprocessor's operating temperature and a control circuit that includes operating point data. The ope... | 04/13/2010 |
| 7681089 | Redundant storage controller system with enhanced failure analysis capability A redundant storage controller system that robustly provides failure analysis information (FAI) to an operator of the system is disclosed. The system includes first and second storage controllers in communication with one another, such as via a PCI-Express link. Whe... | 03/16/2010 |
| 7676600 | Network, storage appliance, and method for externalizing an internal I/O link between a server and a storage controller integrated within the storage appliance chassis A network storage appliance is disclosed. The storage appliance includes a port combiner that provides data communication between at least first, second, and third I/O ports; a storage controller that controls storage devices and includes the first I/O port; a serve... | 03/09/2010 |
| 7673185 | Adaptive SAS PHY configuration A SAS expander adaptively configures a Serial-Attached-SCSI (SAS) PHY to accommodate varying lengths of a cable coupling the PHY to a remote PHY. The expander (a) configures the SAS PHY with settings of an entry of a table of PHY configuration settings, each entry i... | 03/02/2010 |
| 7663957 | Microprocessor with program-accessible re-writable non-volatile state embodied in blowable fuses of the microprocessor A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is bl... | 02/16/2010 |
| 7661014 | Network storage appliance with integrated server and redundant storage controllers A network storage appliance is disclosed. The appliance includes a chassis enclosing a backplane, and a server enclosed in the chassis and coupled to the backplane. The appliance also includes storage controllers enclosed in the chassis, each coupled to the backplan... | 02/09/2010 |
