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Cloaking System Using Optoelectronically Controlled Camouflage
A Cloaking System designed to operate in the visible light spectrum, utilizes optoelectronics and/or photonic components to conceal an object within it.
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| Number | Title | Issue Date |
| 6897530 | Ultra-thin SOI MOS transistors A transistor structure includes a main gate silicon active region having a thickness of less than or equal to 30 nm; and auxiliary gate active regions located on either side of said main gate silicon active region, said auxiliary gate active regions being spaced a d... | 05/24/2005 |
| 6897074 | Method for making single-phase c-axis doped PGO ferroelectric thin films A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrat... | 05/24/2005 |
| 6887799 | Indium oxide conductive film One-transistor ferroelectric memory devices using an indium oxide film (In2O3), an In2O3 film structure, and corresponding fabrication methods have been provided. The method for controlling resistivity in an In2... | 05/03/2005 |
| 6887523 | Method for metal oxide thin film deposition via MOCVD An MOCVD process is provided for forming metal-containing films having the general formula M′xM″(1−x)MyOz, wherein M′ is a metal selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Y, Sc, Yb, Lu, and Gd; ... | 05/03/2005 |
| 6885203 | Wafer level burn-in using light as the stimulating signal An apparatus comprises multiple light sources that are applied to specific locations on the surface of a wafer for the purpose of causing a component on a die to respond as if a digital signal had been applied to the component. The multiple light sources may compris... | 04/26/2005 |
| 6881686 | Low-fluence irradiation for lateral crystallization enabled by a heating source A process of lateral crystallization comprises providing a silicon film on a substrate surface, exposing a localized substrate region at the substrate surface to a laser heating source, and annealing a portion of the silicon film in thermal contact with the localize... | 04/19/2005 |
| 6882714 | Universal call-log system and method for a home network telephone A system and method are provided for maintaining a universal call-log in a Home Network telephone system. The method comprises: transceiving calls on at least one external telephone line; bridging calls to a plurality Home Network endpoints; and, logging the bridged... | 04/19/2005 |
| 6878640 | Method for fabricating silicon targets A method for fabricating silicon tiles and silicon tile targets has been provided, such as may be used in the sputter deposition of thin film transistor (TFT) silicon films. The method describes processes of cutting the tiles, beveling the tiles edges, etching the t... | 04/12/2005 |
| 6875651 | Dual-trench isolated crosspoint memory array and method for fabricating same A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si layer overlying the p-Si substrate; prior to forming the n+ Si bit lines... | 04/05/2005 |
| 6875677 | Method to control the interfacial layer for deposition of high dielectric constant films Methods of forming an interfacial layer on a hydrogen-passivated substrate are provided. These methods utilize atomic layer deposition techniques incorporating metal nitrate-based precursors, such as hafnium nitrate or zirconium nitrate, without introducing a hydrat... | 04/05/2005 |
| 6876521 | Method of making a solid state inductor A solid-state inductor and a method for forming a solid-state inductor are provided. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) thin film overlying the bottom electrode; forming a top electrode overlying the CMR thin... | 04/05/2005 |
| 6873048 | System and method for integrating multiple metal gates for CMOS applications A dual-gate MOSFET with metal gates and a method for setting threshold voltage in such a MOSFET is provided. The method comprises: forming a gate oxide layer overlying first and second channel regions; forming a first metal layer having a first thickness overlying t... | 03/29/2005 |
| 6868025 | Temperature compensated RRAM circuit A temperature compensated RRAM sensing circuit to improve the RRAM readability against temperature variations is disclosed. The circuit comprises a temperature dependent element to control the response of a temperature compensated circuit to generate a temperature d... | 03/15/2005 |
| 6864589 | X/Y alignment vernier formed on a substrate A two dimensional vernier is provided along with a method of fabrication. The two dimensional vernier has a reference array patterned into a substrate, or a material overlying the substrate. An active array is patterned into photoresist overlying the substrate or th... | 03/08/2005 |
| 6861712 | MOSFET threshold voltage tuning with metal gate stack control A stacked metal gate MOSFET and fabrication method are provided. The method comprises: forming a gate oxide layer overlying a channel region; forming a first metal layer having a first thickness overlying the gate oxide layer; forming a second metal layer having a s... | 03/01/2005 |
| 6861687 | Electrically programmable resistance cross point memory structure Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at... | 03/01/2005 |
| 6860939 | Semiconductor crystal-structure-processed mechanical devices, and methods and systems for making Processing and systems to create, and resulting products related to, very small-dimension singular, or monolithically arrayed, semiconductor mechanical devices. Processing is laser performed on selected semiconductor material whose internal crystalline structure bec... | 03/01/2005 |
| 6858514 | Low power flash memory cell and method Flash memory cells are provided with a high-k material interposed between a floating polysilicon gate and a control gate. A tunnel oxide is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided comp... | 02/22/2005 |
| 6852652 | Method of making relaxed silicon-germanium on glass via layer transfer A method of forming a silicon-germanium layer on an insulator includes preparing a silicon substrate; depositing a layer of silicon-germanium on the silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions in the silicon-germanium laye... | 02/08/2005 |
| 6849891 | RRAM memory cell electrodes A RRAM memory cell is formed on a silicon substrate having a operative junction therein and a metal plug formed thereon, includes a first oxidation resistive layer; a first refractory metal layer; a CMR layer; a second refractory metal layer; and a second oxidation ... | 02/01/2005 |
| 6849564 | 1R1D R-RAM array with floating p-well A low-capacitance one-resistor/one-diode (1R1D) R-RAM array with a floating p-well is provided. The fabrication method comprises: forming an integrated circuit (IC) substrate; forming an n-doped buried layer (buried n layer) of silicon overlying the substrate; formi... | 02/01/2005 |
| 6849467 | MOCVD of TiO2 thin film for use as FeRAM H2 passivation layer A method of forming an H2 passivation layer in an FeRAM includes preparing a silicon substrate; depositing a layer of TiOx thin film, where 0 | 02/01/2005 |
| 6841833 | 1T1R resistive memory A drain loaded 1T1R resistive memory device and 1T1R resistive memory array are provided. The resistive memory array comprises an array of drain loaded 1T1R resistive memory device structures. Word lines are connected across transistor gates, while a resistive eleme... | 01/11/2005 |
| 6841844 | Air gaps copper interconnect structure An inter-level insulator structure is provided having an effective insulator dielectric constant approaching 1. An embodiment of the inter-level insulator comprises a first metal layer comprising a first plurality of metal lines; a second metal layer comprising a se... | 01/11/2005 |
| 6833572 | Electrode materials with improved hydrogen degradation resistance An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platin... | 12/21/2004 |
| 6830965 | Semiconductor device and a method of creating the same utilizing metal induced crystallization while suppressing partial solid phase crystallization A metal induced crystallization process is provided which employs an amorphous silicon film precursor deposited by physical vapor deposition, wherein the precursor film does not readily undergo crystallization by partial solid phase crystallization. Using this physi... | 12/14/2004 |
| 6825086 | Strained-silicon channel CMOS with sacrificial shallow trench isolation oxide liner A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method comprises: forming a Si substrate; forming a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SG... | 11/30/2004 |
| 6825058 | Methods of fabricating trench isolated cross-point memory array Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the r... | 11/30/2004 |
| 6825106 | Method of depositing a conductive niobium monoxide film for MOSFET gates A method is provided to deposit niobium monoxide gates. An elemental metal target, or a composite niobium monoxide target is provided within a sputtering chamber. A substrate with gate dielectric, for example silicon dioxide or a high-k gate dielectric, is provided ... | 11/30/2004 |
| 6825519 | Selectively deposited PGO thin film and method for forming same A memory device formed from selectively deposited PGO and a method for selectively forming a Pb5Ge3O11 (PGO) thin film memory device are provided. The method comprises: forming a silicon (Si) substrate; forming a silicon oxide film o... | 11/30/2004 |
| 6818484 | Method of forming predominantly <100> polycrystalline silicon thin film transistors A method is provided to produce thin film transistors (TFTs) on polycrystalline films having a single predominant crystal orientation. A layer of amorphous silicon is deposited over a substrate to a thickness suitable for producing a desired crystal orientation. Lat... | 11/16/2004 |
| 6809801 | 1:1 projection system and method for laser irradiating semiconductor films A 1:1 laser projection system and method are provided for laser irradiating a semiconductor film. The method comprises: exposing a mask to a beam of laser light; projecting laser light passed through the mask by a factor of one; exposing the area of a semiconductor ... | 10/26/2004 |
| 6768603 | Precompensation technique and MTR code for high data rate recording A method for write-precompensating a waveform for magnetically recording a waveform on a magnetic medium is disclosed. A user data stream is encoded into an encoded data stream so that the encoded data stream has no tribits and no consecutive dibits. No delay is app... | 07/27/2004 |
