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Microwave Oven With Removable Storage Cassette in Dashboard of Motor Vehicle
A microwave oven adapted for use within a motor vehicle dashboard area. The microwave oven has a removable storage cassette, and slidable platforms for securing and serving containers of beverages and foods.
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| Number | Title | Issue Date |
| 8176304 | Mechanism for performing function level reset in an I/O device An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may b... | 05/08/2012 |
| 8169236 | Frequency detection mechanism for a clock generation circuit A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency mul... | 05/01/2012 |
| 8156286 | Processor and method for using an instruction hint to prevent hardware prefetch from using certain memory accesses in prefetch calculations A microprocessor includes a cache memory, a prefetch unit, and detection logic. The prefetch unit may be configured to monitor memory accesses that miss in the cache and to determine whether to prefetch one or more blocks of memory from a system memory based upon pr... | 04/10/2012 |
| 8154275 | Apparatus and method for testing sense amplifier thresholds on an integrated circuit An apparatus and method for testing sense amplifier threshold voltages on an integrated circuit includes one or more sense amplifier modules each including a number of sense amplifier circuits, a voltage generator unit, and detection logic. The voltage generator uni... | 04/10/2012 |
| 8149001 | Low cost fingerprint sensor system Low cost fingerprint system having a single chip solution includes a circuit board, a fingerprint sensor array fabricated onto a first surface of the circuit board, and an integrated circuit die for processing information received from the fingerprint sensor array i... | 04/03/2012 |
| 8130572 | Low power memory array column redundancy mechanism A low power memory array column redundancy mechanism includes a memory unit having a memory array and a multiplexer unit. The memory array includes a plurality of columns, which includes a plurality of data columns and one or more unused columns. The multiplexer uni... | 03/06/2012 |
| 8125250 | Frequency detection mechanism for a clock generation circuit A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency mul... | 02/28/2012 |
| 8125211 | Apparatus and method for testing driver writeability strength on an integrated circuit An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage on... | 02/28/2012 |
| 8117498 | Mechanism for maintaining cache soft repairs across power state transitions A processor core includes one or more cache memories and a repair unit. The repair unit may repair locations in the cache memories identified as having errors during an initialization sequence. The repair unit may further cause information corresponding to the repai... | 02/14/2012 |
| 8032673 | Transaction ID filtering for buffered programmed input/output (PIO) write acknowledgements A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactons sources. Each PIO write operation may include a source identifier that identifies the ... | 10/04/2011 |
| 8032670 | Method and apparatus for generating DMA transfers to memory In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface ac... | 10/04/2011 |
| 8031731 | System for sharing a network port of a network interface including a link for connection to another shared network interface A system for sharing a network port of a network interface includes a plurality of processing units, a first network interface unit coupled to a first portion of the plurality of processing units, a second network interface unit coupled to a different portion of the... | 10/04/2011 |
| 8028130 | Pipeline structure for a shared memory protocol A method and apparatus for implementation of a pipeline structure for data transfer. A request is received from a first domain to access a second domain during a first clock cycle. A pipeline structure is used to perform at least a portion of the request during a su... | 09/27/2011 |
| 8028103 | Method and apparatus for generating secure DAM transfers In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive t... | 09/27/2011 |
| 8024526 | Multi-node system with global access states A system may include several nodes coupled by an inter-node network configured to convey coherency messages between the nodes. Each node may include several active devices coupled by an address network and a data network. The nodes implement a coherency protocol suc... | 09/20/2011 |
| 8019907 | Memory controller including a dual-mode memory interconnect A memory controller including a dual-mode memory interconnect includes an input/output (I/O) circuit including a plurality of input buffers and a plurality of output drivers. The I/O circuit may be configured to operate in one of a first mode and a second mode depen... | 09/13/2011 |
| 8006110 | Method and apparatus for keeping a virtual private network session active on a portable computer system including wireless functionality An apparatus for keeping a VPN session alive on a portable computer system such as a laptop computer includes a processor that executes instructions that implement application software. The laptop computer system also includes a wireless module that may communicate ... | 08/23/2011 |
| 7984338 | Program counter (PC) trace In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comp... | 07/19/2011 |
| 7977998 | Apparatus and method for testing level shifter voltage thresholds on an integrated circuit An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supp... | 07/12/2011 |
| 7962733 | Branch prediction mechanisms using multiple hash functions In one embodiment, the branch prediction mechanism includes a first storage including a first plurality of locations for storing a first set of partial prediction information. The branch prediction mechanism also includes a second storage including a second pluralit... | 06/14/2011 |
| 7934124 | Self-contained densely packed solid-state storage subsystem A rack mountable solid-state storage subsystem includes a plurality of interface units and a plurality of data storage modules to implement a mass storage device. Each of the interface units may be coupled to a plurality of communication ports for connection to a ho... | 04/26/2011 |
| 7930602 | Method and system for performing a double pass NTH fail bitmap of a device memory A method for performing a double pass nth fail bitmap of a memory array of a device under test includes a memory built-in test (MBIST) unit reading previously written data from each location of the memory array during a first pass, and detecting a failure... | 04/19/2011 |
| 7929549 | Method and apparatus for scrambling data for control of high-speed bidirectional signaling A memory subsystem includes a master controller that includes a pseudo random bit sequence (PRBS) generator having a plurality of output taps and an exclusive-OR (XOR) unit. The memory subsystem also includes a memory device that is coupled to the master controller ... | 04/19/2011 |
| 7912082 | Shared virtual network interface A system includes one or more processing units coupled to a network interface unit. The network interface unit may include a network port for connection to a network and a virtual interface that may be configured to distribute an available communication bandwidth of... | 03/22/2011 |
| 7890909 | Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow An automatic custom block composition tool for composing custom blocks of an integrated circuit (IC) design that may include non-standard library cells. The tool includes program instructions that are executable to create and use a placement control file that includ... | 02/15/2011 |
| 7890138 | Mechanism for remotely accessing a portable computer including wireless communication functionality A portable computer system such as a laptop computer system includes a computing subsystem that includes a processor that may execute instructions that implement application software, and a storage coupled to the processor that may store information. The laptop comp... | 02/15/2011 |
| 7890075 | Mechanism for controlling amplifier gain in a radio receiver A radio receiver such as a frequency modulation (FM) receiver, for example, includes a radio frequency (RF) amplifier having an adjustable gain output. The RF amplifier may be configured to receive and amplify an incoming RF signal. The receiver also includes an int... | 02/15/2011 |
| 7890072 | Wireless communication apparatus for estimating(C/I) ratio using a variable bandwidth filter A wireless communication apparatus includes a mechanism for estimating carrier-to-interference (C/I) ratio using a variable bandwidth filter. More particularly, the wireless communication apparatus includes a channel equalization unit coupled to a C/I ratio estimati... | 02/15/2011 |
| 7882309 | Method and apparatus for handling excess data during memory access A computer system includes a system memory and a processor having one or more processor cores and a memory controller. The memory controller may control data transfer to the system memory. The processor further includes a cache memory such as an L3 cache, for exampl... | 02/01/2011 |
| 7878861 | Energy storage module including a connector having unique pin configuration An energy storage module includes a motherboard and a connector that may convey power, ground, and I/O signals to and from the motherboard. The connector includes a non-metallic housing that includes a plurality of sections, each having a corresponding connector con... | 02/01/2011 |
| 7865770 | Processor including efficient signature generation for logic error protection A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units operating in lock-step. The processor core also includes signature generation logic that may generate, concurrently wit... | 01/04/2011 |
| 7861066 | Mechanism for predicting and suppressing instruction replay in a processor A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution units. The scheduler may also cause instruction operations that are de... | 12/28/2010 |
| 7861041 | Second chance replacement mechanism for a highly associative cache memory of a processor A cache memory system includes a cache memory and a block replacement controller. The cache memory may include a plurality of sets, each set including a plurality of block storage locations. The block replacement controller may maintain a separate count value corres... | 12/28/2010 |
| 7843244 | Low latency synchronizer circuit A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input ... | 11/30/2010 |
| 7836259 | Prefetch unit for use with a cache memory subsystem of a cache memory hierarchy A prefetch unit for use with a cache subsystem. The prefetch unit includes a stream storage coupled to a prefetch unit. The stream storage may include a plurality of locations configured to store a plurality of entries each corresponding to a respective range of pre... | 11/16/2010 |
| 7835468 | Impulse detection and reduction in a frequency modulation radio receiver A radio receiver includes a processing unit that may generate a respective phase value corresponding to each of a plurality of digital samples of a received complex frequency modulation (FM) signal. The receiver also includes an impulse unit that may detect whether ... | 11/16/2010 |
| 7834790 | Communication device including a power reduction mechanism A communication device includes a communication port that includes a digital to analog converter (DAC) that may be configured to output for transmission an analog signal that corresponds to a digital input such as link data that is to be transmitted on a physical li... | 11/16/2010 |
| 7783954 | System for controlling high-speed bidirectional communication A system for controlling high-speed bidirectional communication includes a slave device such as a memory device, for example, coupled to a master device such as a memory controller, for example. The master device may be configured to control data transfer between th... | 08/24/2010 |
| 7779285 | Memory system including independent isolated power for each memory module A memory system including independent power for each memory module. The memory system includes a plurality of memory modules each including a plurality of memory chips configured to store data. The memory system further includes a power conversion unit coupled to pr... | 08/17/2010 |
| 7765503 | Half cycle common path pessimism removal method A design tool for reducing half-cycle common path pessimism includes program instructions storable on a computer readable medium. The program instructions may be executable by a processor to receive a timing report for the IC. For each source clock path and destinat... | 07/27/2010 |
